Logical Instructions in 8085

In this lecture, we will learn about the Logical Instructions in 8085 used for programming. We will learn all the logical instructions with a very detailed analysis. So before starting each instruction, we will know what logical instructions are available in the 8085 microprocessor.

So let’s start with the group of instructions and its name below.

Also Read:

Logical Instructions in 8085

In the 8085 microprocessor, logical instructions perform various logical operations with the content of the accumulator.

AND, OR, XORAny 8-bit number, or the contents of a register or of a memory location can be logically ANDed, ORed, or XORed with the content of the accumulator. The results are stored in the accumulator.
RotateEach bit in the accumulator can be shifted either left or right to the next position.
CompareAny 8-bit number, or the content of a register, or a memory location can be compared for equally, greater than, or less than, with the contents of the accumulator.
ComplementThe contents of the accumulator can be complemented. All 0s are replaced by 1s and all 1s are replaced by 0s.

The logical instructions of 8085 include the following instructions:

ANA RANA MANI dataORA R
ORA MORA dataXRA RXRA M
XRI dataCMACMCSTC
CMP RCMP MCPI dataRLC
RRCRALRAR

Now we will discuss each logical instruction of 8085 in detail.

ANA R

MnemonicANA R
OperationA = A AND R
No. of Bytes1 byte
Machine cycles1 (OF)
AlgorithmA A ∧ R
FlagsS, Z, and P are modified to reflect the result of the operation. The carry flag is reset and the AC flag is set.
Addressing ModeRegister addressing mode
T-states4
DescriptionLogically AND register with accumulator.
This instruction will logically AND the contents of the specified register with the contents of the accumulator and the result will be stored in the accumulator.
The operation of ANDing is performed bit by bit. i.e. B0 bit of the accumulator is ANDed with the B0 bit of the specified register, and so on up to the B7 bit of the accumulator is ANDed with the B7 bit of the specified register.
Example
ANA B
Let A = 65 H and B = 82 H and instruction ANA B is executed.

The example of intruction ANA R are:

ANA AANA BANA CANA D
ANA EANA HANA L

ANA M

MnemonicANA M
OperationA = A AND M
No. of Bytes1 byte
Machine cycles2 (OF + MR)
AlgorithmA A ∧ M
FlagsS, Z, and P are modified to reflect the result of ANDing. The carry flag is reset and the AC flag is set.
Addressing ModeIndirect addressing mode
T-states7 (4 + 3)
DescriptionLogically AND memory with accumulator.
The contents of the memory location pointed by the HL register pair are ANDed with the contents of the accumulator and the result is stored in the accumulator. The HL register pair acts as a memory pointer.
Example
ANA M
Let A = 4A H, H = 20 H, L = FF H, at memory location 20FF : EF H is stored and instruction ANA M is executed.

ANI Data

MnemonicANI Data
OperationA = A AND data
No. of Bytes2 bytes
1st Byte: Opcode
2nd Byte: 8-bit data
Machine cycles1 (OF +MR)
AlgorithmA A ∧ Data
FlagsS, Z, and P are modified to reflect the result of the operation. CY is reset and AC is set.
Addressing ModeImmediate Addressing mode
T-states7 (4+3)
DescriptionLogically AND immediate data with accumulator.
This instruction logically ANDs the content of the accumulator with the 8-bit data specified in the instruction. The result is stored in the accumulator.
The ANDing is done bitwise.
Example
ANI 0FH
Let A = F7 and instruction ANI OF is executed.

ORA R

MnemonicORA R
OperationA = A OR R
No. of Bytes1 byte
Machine cycles1 (OF)
AlgorithmA A ∨ R
FlagsS, Z, and P are modified to reflect the result of the operation. AC and CY are reset
Addressing ModeRegister Addressing mode
T-states4
DescriptionLogically OR contents of specified register with accumulator.
This instruction will logically OR the contents of the specified register with the accumulator and the result is stored in the accumulator.
The ORing is done bit by bit. i.e. B0 bit of register with B0 bit of accumulator, B1 bit of register with B1 bit of register with b1 bit of accumulator, and so on up to B7 bit.
The register R can be any general-purpose register like A, B, C, D, E H, or L.
Example
ORA C
Let A = A2 H and C = B5 H and instruction ORA C are executed.

The examples of the instruction ORA R are:

ORA AORA BORA CORA D
ORA EORA HORA L

ORA M

MnemonicORA M
OperationA = A OR M
No. of Bytes1 byte
Machine cycles2 (OF + MR)
AlgorithmA A ∨ M or
A A ∨ (HL)
FlagsS, Z, and P are modified to reflect the result of the operation. AC and CY are reset
Addressing ModeIndirect Addressing mode
T-states7 (4+3)
DescriptionLogically OR contents of memory with accumulator.
This instruction will logically OR the contents of the accumulator with the contents of the memory location and the result is stored in the accumulator. The address of the memory location is given by the HL register pair.
The ORing operation is done bitwise.
Example
ORA M
Let A = AA H, H = AA H, L = ABH, at memory location AAAB: 55H data stored, and the instruction ORA M is executed.

ORI Data

MnemonicORI Data
OperationA = A OR Data
No. of Bytes2 byte
Machine cycles2 (OF + MR)
AlgorithmA A ∨ Data
FlagsS, Z, and P are modified to reflect the result of the operation. AC and CY are reset
Addressing ModeImmediate Addressing mode
T-states7 (4+ 3)
DescriptionLogically OR immediate data with accumulator.
The contents of the accumulator are ORed with 8-bit data specified along with the instruction and the result is stored in the accumulator.
Example
ORI 20H
Let A = 55 and instruction ORI 20 H is executed.

XRA R

MnemonicXRA R
OperationA = A R
No. of Bytes1 byte
Machine cycles1 (OF)
AlgorithmA A XOR R or
A A R
FlagsS, Z, and P are modified to reflect the result of the operation. AC and CY are reset
Addressing ModeRegister Addressing mode
T-states4
DescriptionXOR register with accumulator.
This instruction will XOR the content of the accumulator with the content of the register specified and the result will be stored in the accumulator.
The XORing operation is done bit by bit. i.e. B0 bit of the register is XORed with the B0 bit of the accumulator and so on.
R may be any general-purpose register like A, B, C, D, E, H, and L.
Example
XRA D
Let A =77H and D = 06H and instruction XRA D is executed.

XRA M

MnemonicXRA M
OperationA = A M
No. of Bytes1 byte
Machine cycles2 (OF + MR)
AlgorithmA A XOR M or
A A M
FlagsS, Z, and P are modified to reflect the result of the operation. AC and CY are reset
Addressing ModeIndirect Addressing mode
T-states7 (4+3)
DescriptionLogically XOR data is in memory with an accumulator.
This instruction will logically XOR the content of the memory location with the contents of the accumulator and the result is stored in the accumulator. the HL register pair give the address of the memory location.
The operation of XORing is performed bitwise.
Example
XRA M
Let A =A5 H, H = 50 H, L = 05 H, at memory location 5005: 50H is sorted, and the instruction XRA M is executed.

XRI Data

MnemonicXRI Data
OperationA = A data
No. of Bytes2 byte
1st Byte: Opcode
2nd byte: 8-bit data
Machine cycles2 (OF + MR)
AlgorithmA A XOR data or
A A data
FlagsS, Z, and P are modified to reflect the result of the operation. AC and CY are reset
Addressing ModeImmediate Addressing mode
T-states7 (4+3)
DescriptionLogically XOR immediate data with an accumulator.
This instruction will logically XOR the contents of the accumulator with the 8-bit data specified along the instruction. The result is stored in the accumulator.
The XORing operation is done bitwise.
Example
XRI 2FH
This instruction will XOR the contents of the accumulator with data 2F H and the result will be stored in the accumulator.

CMA

MnemonicCMA
OperationA =
No. of Bytes1 byte
Machine cycles1 (OF)
AlgorithmA
FlagsNo flags are modified
Addressing ModeImplied addressing mode
T-states4
DescriptionComplement accumulator.
This instruction complements the content of the accumulator and the result is placed in the accumulator.
The complement is performing an inversion operation of each bit i.e. 0 will be replaced by 1 and 1 will be replaced by 0.
Example
CMA
If A = ABH and the instruction CMA is executed.
After the CMA instruction is executed A will contain 54H and there will be no change in the flag status.

CMC

MnemonicCMC
OperationCY =
No. of Bytes1 byte
Machine cycles1 (OF)
AlgorithmCY
FlagsOnly the carry flag is complemented. No other flags are affected.
Addressing ModeImplied addressing mode
T-states4
DescriptionComplemented the carry flag.
This instruction complements the carry flag. i.e. if the carry flag = 1 the instruction will reset it and if CY flag = 0 the instruction will be set to 1.
Example
CMC
CMC Instruction

STC

MnemonicSTC
OperationCY = 1
No. of Bytes1 byte
Machine cycles1 (OF)
AlgorithmCY 1
FlagsOnly the carry flag is set. No other flags are modified.
Addressing ModeImplied addressing mode
T-states4
DescriptionSet the carry flag.
This instruction sets the carry flag.
Example
CMC
STC instruction

CMP R

MnemonicCMP R
Operation(A – R) A compare R
No. of Bytes1 byte
Machine cycles1 (OF)
AlgorithmA Compare R
FlagsS, Z, and P are modified to reflect the status of subtraction, and Z, CY are used to indicate the result of comparison.
Addressing ModeRegister addressing mode
T-states4
DescriptionCompare register with accumulator.
This instruction compares the contents of the accumulator with the content of the register specified.
The operation of comparing is performed by subtracting the register contents from the accumulator contents.
The contents of the register or accumulator are not altered.
The result of the comparison is indicated by setting the flags as follows:
If A > R : CY = 0 and Z = 0
If A = R : Cy = 0 and Z = 1
If A < R : CY = 1 and Z = 0
The S, P, and AC flags are modified to reflect the status of subtraction, or Z, and CY are used to indicate the result of the comparison.
The register R is any general-purpose register like A, B, C, D, E, H, or L.
Example
1. CMP B
2. CMP C
3. CMP D
1. Let A = 20H, B = 10H. Now if the instruction CMP B is executed. Then the status of flags will be CY = 0 and Z = 0 to indicate A > B.
2. Let A = 10H, C = 10H. Now if the instruction CMP C is executed. Then the status of flags will be CY = 0 and Z = 1 to indicate A = B.
3. Let A = 10H, D = 20H. Now if the instruction CMP D is executed. Then the status of flags will be CY = 1 and Z = 0 to indicate A < B.

The examples of the instruction CMP R are:

CMP ACMP BCMP CCMP D
CMP ECMP HCMP L

CMP M

MnemonicCMP M
Operation(A – M)
No. of Bytes1 byte
Machine cycles2 (OF + MR)
AlgorithmA Compare M
FlagsZ and CY flags are used to indicate the result of the comparison. S, P AC flags are modified to reflect the status of subtraction.
Addressing ModeIndirect addressing mode
T-states7 ( 4+3)
DescriptionCompare memory with accumulator.
This instruction compares the contents of the accumulator and memory location contents. The HL register pair gives the address of the memory location.
The contents of the accumulator and memory location are not altered.
The result of the comparison is indicated by setting the flags as follows:
If A > M : CY = 0 and Z = 0
If A = M : Cy = 0 and Z = 1
If A < M : CY = 1 and Z = 0
The S, P, and AC flags are modified to reflect the status of subtraction, or Z, and CY are used to indicate the result of the comparison.
Example
CMP M
Let A = 20H, H = C0H, L = 02H at memory location C002: 10H is stored, and the instruction CMP M is executed.
The flag staus will be as follows:
CY = 0, Z = 0, P = 0 S = 0, AC = 0

CPI Data

MnemonicCPI Data
Operation(A – data)
No. of Bytes2 byte
1st byte: Opcode
2nd byte: 8-bit data
Machine cycles2 (OF + MR)
AlgorithmA Compare data
FlagsZ and CY flags are used to indicate the result of the comparison. S, P AC flags are modified to reflect the status of subtraction.
Addressing ModeImmediate addressing mode
T-states7 ( 4+3)
DescriptionCompare immediate data with the accumulator.
This instruction subtracts the 8-bit data given in the instruction from the content of the accumulator and sets the condition flags as a result of subtraction.
If sets the zero flag if A = data and sets the carry flag if A < data.
The contents of the accumulator and data are unchanged, as the result of comparison is indicated by the flags.
Example
CPI 30H
Let A = 10H and the instruction CPI 30H is executed.
The flag staus will be as follows:
CY = 1, Z = 0, P = 0 S = 1, AC = 0

RLC

MnemonicRLC
OperationFor n = 0 to 6, Bn+1 = Bn
B0 = CY = B7
No. of Bytes1 byte
Machine cycles1 (OF )
AlgorithmBn+1 ← Bn (for n = 0 to 6)
B0 B7
CY B7
FlagsOnly the carry flag is modified. Bit B7 is copied to the carry flag. no other flags are modified.
Addressing ModeImplied addressing mode
T-states4
DescriptionRotate Accumulator left.
This instruction will rotate the content of the accumulator to the left by 1 bit. i.e. it shifts the bits left by one position. B0 will be transferred to B1, b1 to B2, and so on B6 to b7, B7 to B0 as well as the carry flag. The operation is shown in the figure below.
RLC Instruction
Example
Let A = 1F H and instruction RLC is executed. the content of the accumulator will be rotated by 1 bit to the left and the result will be stored in the accumulator
i.e. A = 3E H
RLC

RRC

MnemonicRRC
OperationFor n = 0 to 6, Bn = Bn+1
B7 = CY = B0
No. of Bytes1 byte
Machine cycles1 (OF )
AlgorithmBn ← Bn+1 (for n = 0 to 6)
B7 B0
CY B0
FlagsOnly the carry flag is modified. All other flags are unmodified.
Addressing ModeImplied addressing mode
T-states4
DescriptionRotate Accumulator Right.
This instruction rotates the contents of the accumulator to the right by one position. Bit B0 is placed in B7 as well as CY flag as shown in the figure below.
RRC instruction
Example
A = 1CH and
CY = 1
After the execution of the instruction, the accumulator contents will be 0E H and the carry flag will be reset.
RRC operation

RAL

MnemonicRAL
OperationFor n = 0 to 6, Bn+1 = Bn
CY = B7
B0 = CY
No. of Bytes1 byte
Machine cycles1 (OF )
AlgorithmBn+1 ← Bn (for n = 0 to 6)
CY B7
B0 CY
FlagsOnly the carry flag is modified. All other flags are unmodified.
Addressing ModeImplied addressing mode
T-states4
DescriptionRotate Accumulator left through Carry.
This instruction will rotate the content of the accumulator to the left by 1-bit position along with carry. B7 is placed in CY and CY is placed in bit B0. The below figure shows the operation.
RAL instruction
Example
Let A = 0EH, CY =1. After execution of the instruction, the contents of the accumulator will be 1DH ad CY = 0.
RAL operation

RAR

MnemonicRAR
OperationFor n = 0 to 6, Bn = Bn+1
B7 = CY
CY = B0
No. of Bytes1 byte
Machine cycles1 (OF )
AlgorithmBn ← Bn+1 (for n = 0 to 6)
CY B0
B7 CY
FlagsOnly the carry flag is modified. All other flags are unmodified.
Addressing ModeImplied addressing mode
T-states4
DescriptionRotate Accumulator Right through Carry.
This instruction will rotate the content of the accumulator right by 1-bit position along with carry. B0 is placed in CY and CY is placed in bit B7. The below figure shows the operation.
RAR Instruction
Example
Let A = 0EH and CY = 1 and the instruction RAR is executed. After execution of the instruction accumulator contents will be (1000 0111) 87H and the carry flag will be reset.
RAR operation

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Hello friends, my name is Trupal Bhavsar, I am the Writer and Founder of this blog. I am Electronics Engineer(2014 pass out), Currently working as Junior Telecom Officer(B.S.N.L.) also I do Project Development, PCB designing and Teaching of Electronics Subjects.

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