In this lecture, we will learn about the Half adder, its circuit diagram, the truth table of half adder, and the K-map of the half adder in a very detailed analysis.

Adding two binary digits is the most basic operation performed by digital computers. For this addition, there are binary adders used.

There are two types of binary adders:

In this section, we are going to learn digital circuits which are used to add two binary numbers called Half adders. We will learn the full adder in the next lecture.

**What is Half Adder**

Half Adder is a combinational logic circuit with two inputs and two outputs. It is the basic building block for the addition of two single-bit numbers. This combinational circuit has two outputs namely “carry” and “Sum”.

**Block diagram of Half Adder**

The basic block diagram and circuit diagram of the Half adder are shown in the below figure.

The half adder circuit is designed to add two single-bit binary numbers A and B.

**Operation of Half Adder**

The Half adder adds two binary digits according to the rules of binary addition. These rules are as follows:

```
0 + 0 = 0
0 + 1 = 1
1 + 0 = 1
1 + 1 = 10 (Sum = 0 & Carry = 1)
```

These binary addition rules show that the first three operations result in a sum with a length of one digit, whereas the last operation (1 and 1) results in a sum with a length of two digits. Here, the LSB (least significant bit) is referred to as the sum (which is 0), and the MSB (most significant bit) of this result is referred to as a carry (which is 1).

**Truth Table of Half Adder**

A truth table shows how a logic circuit’s inputs and outputs relate to one another and describes how the circuit works. The half adder truth table is provided below:

Inputs | Outputs | ||
---|---|---|---|

A | B | S (Sum) | C (Carry) |

0 | 0 | 0 | 0 |

0 | 1 | 1 | 0 |

1 | 0 | 1 | 0 |

1 | 1 | 0 | 1 |

**K-Map for Half Adder**

We can use the K-Map (Karnaugh Map), a method for simplifying Boolean algebra, to determine equations of the sum bit (S) and the output carry bit (C) of the half adder circuit.

K-maps for carry and sum outputs are shown in the figure below:

**Characteristic Equations of Half-Adder**

The characteristic equations of half adder, i.e., equations of sum (S) and carry (C) are obtained according to the rules of binary addition. These equations are given below:

The sum (S) of the half-adder is the XOR of A and B. Thus,

`Sum, \mathbf{S = \overline A B + A \overline B = A \oplus B}`

The carry (C) of the half-adder is the AND of A and B. Therefore,

`and Carry, \mathbf{C = A\cdot B}`

**Circuit Diagram of Half Adder**

The circuit of the half adder is also shown in the below figure.

**Half Adder using Nand Gate**

NAND gates can be used to build the half-adder circuit. The NAND gate is basically a universal gate, which means that it may be used to create any digital circuit. The below figure depicts the implementation of a half adder with a NAND gate.

From the circuit of a half adder with a NAND gate, it is clear that a minimum of 5 NAND gates are required to design a half adder circuit.

The operation of the half-adder circuit with NAND gates can be better understood by using the following equations:

Sum,S=((Aâ‹…(AB)â€²)â€²â‹…(Bâ‹…(AB)â€²)â€²)â€²Sum,S=((Aâ‹…(AB)â€²)â€²â‹…(Bâ‹…(AB)â€²)â€²)â€²

â‡’Sum,S=((Aâ‹…(AB)â€²)â€²)â€²+((Bâ‹…(AB)â€²)â€²)â€²â‡’Sum,S=((Aâ‹…(AB)â€²)â€²)â€²+((Bâ‹…(AB)â€²)â€²)â€²

â‡’Sum,S=Aâ‹…(AB)â€²+Bâ‹…(AB)â€²â‡’Sum,S=Aâ‹…(AB)â€²+Bâ‹…(AB)â€²

â‡’Sum,S=Aâ‹…(Aâ€²+Bâ€²)+Bâ‹…(Aâ€²+Bâ€²)â‡’Sum,S=Aâ‹…(Aâ€²+Bâ€²)+Bâ‹…(Aâ€²+Bâ€²)

â‡’Sum,S=AAâ€²+ABâ€²+Aâ€²B+BBâ€²â‡’Sum,S=AAâ€²+ABâ€²+Aâ€²B+BBâ€²

âˆ´ Sum,S=ABâ€²+Aâ€²B=AâŠ•Bâˆ´Sum,S=ABâ€²+Aâ€²B=AâŠ•B

Similarly, the carry bit (C) is given by,

Carry,C=((AB)â€²)â€²=ABCarry,C=((AB)â€²)â€²=AB

Hence, in this way, we can also realize the half-adder in NAND logic.

**Disadvantages of Half Adder**

The principle of adding two 2-bit numbers A and B is shown in the above figure.

Let Number A = A_{1} A_{0}

and Number B = B_{1} B_{0}

Then the addition should take place as follows:

A half-adder can add A_{0} and B_{0} to produce S_{0} and C_{0}. But the addition of the next bit requires the addition of A_{1}, B_{1}, and C_{0}. The addition of three bits is not possible to perform by using a half adder. Hence we cannot use a half-adder in practice.

**Applications of Half Adder**

The following are some significant uses for half adder:

- In the ALU (Arithmetic Logic Unit) of computer processors, half-adders are used to add binary bits.
- To create a full adder circuit, a half adder is used.
- Calculators employ a half-adder.
- Tables and addresses are computed using a half-adder.