what is hazard in digital electronics | Types of hazards in digital electronics


In this lecture we are going to learn about what is Hazard in digital electronics, various types of Hazard in digital electronics, How hazard is introduced in digital electronics, and how hazards can be eliminated from digital circuits. So let’s discuss each topic one by one in a detailed manner.

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What is Hazard in Digital Electronics

Whenever undesirable or unwanted transitions in the output signal of digital circuits then we can call them Hazard.

Hazards are unwanted switching transients that appear at the output of a circuit due to different propagation delays of different paths.

Here transients mean, the unwanted switching which appears in the output, will be very short in duration, like a glitch that will be removed after some time.

Such a transient is also called a glitch or a spike that occurs due to the Hazardous behavior of a circuit.

Types of Hazard in Digital Electronics

There are three types of hazard which are occurred in any digital circuit:

  1. Static hazard
  2. Dynamic hazard
  3. Essential hazard
hazards in digital electronics

Static Hazard

Static Hazard is those where the signal level should have been constant but it changes for a small amount of time.

For example, if the signal level is ‘1’ for all time but due to some static hazard it will become from ‘1’ to  ‘0’ for a small amount of time, or if a signal level is ‘0’  for all time but due to some static hazard it will become from ‘0’ to ‘1’.

Note: if any static hazard comes in digital circuits then both static ‘1’ and static ‘0’ hazard will come in the circuit simultaneously. Only static ‘1’ or only static ‘0’ hazard will not generate in a digital circuit.

Static 1 Hazard:

Static 1 hazard occurs due to different delays experienced by the signal through the Gates connected in circuits.

Static 1 hazard always occurs in SOP (Sum of Product) terms.

Let’s consider one example here to know more about the static hazard

Example: F(A, B, C) = Σm (3, 4, 5, 7) 


Now make a K-map and its logic circuit like the below figure:

let’s assume that each gate in the logic circuit having some equal propagation delay.

Consider initially, if A=C=1 then B → 1 to 0 then,

Case 1: A=B=C=1 then check the result, D=AB’=0 and E=BC=1 then F=D+E=1 

Case 2: A=C=1 and B=0 then D=AB’=1 and E=BC=0 then F=D+E=1

So in both, the case Output should be 1 but now we will see the effect of the propagation delay in the below waveform:.

waveform of static 1 hazard

If you analyze the above figure then, you can see that the output should be always at logic 1 but due to propagation delay of the logic gates, we have observed the static 1 hazard.

Static 0 Hazard:

Static 0 hazard occurs due to different delays experienced by the signal through the Gates connected in circuits.

Static 0 hazard always occurs in POS (Product of Sum) terms.

The above analysis for the Static 0 hazard can be done with the POS terms. then you will find that in the POS terms you will get the static 0 hazard in the output of the waveform with the same analysis. 

I will not redraw the above analysis for the static 0 hazard, but if you analyze the above example then you will get easily identified.

How to eliminate static Hazard in digital circuit?

As you have seen in the above example of static 1 hazard, now to eliminate static hazard from the digital circuit then you have to add the redundant terms in the logical expression.

After adding the redundant terms you will find that static hazard will remove.

eliminate static hazard

Now if you see the above logical expression shown in the figure then the last terms which we have added as redundant are AC terms which are always giving constant output as we have taken A=C=1 always.

So, there will be no effect of the Not gate propagation delay in the above example.

So we can say that to remove the static hazard from the logical circuits we have to add redundant terms in the expression. 

Minimizing the logical expression in the lowest possible expression is not always necessary as they produce static hazards, so sometimes it is beneficial to add redundant terms in the logical expression.

Static hazard can be eliminated by adding redundant terms which increases the hardware but removes the glitch.

when two max terms are covered by different grouping and the input switches such that we jump from one max term to the other there is glitch formation, and to remove that glitch we must add a redundant term that covers both the max terms.

Dynamic Hazard

Dynamic Hazard occurs during a multilevel circuit where the output must make a transition from 0 to 1 or from 1 to 0 but the output makes multiple transitions then settles to a final value.

Dynamic hazard occurs when the output changes for 2 adjacent input combinations while changing, the output should change on just one occasion . But it’s going to change three or more times briefly intervals due to different delays in several paths.

Dynamic hazards occur only in multilevel circuits.

Dynamic hazards are more complex to resolve but note that if all static hazards are eliminated from a circuit, then dynamic hazards cannot occur

Essential Hazard

Another sort of hazard which will occur in asynchronous sequential circuits is named an essential hazard.

This type of hazard is caused by unequal delays along two or more paths that originate from an equivalent input.

An excessive delay through an inverter circuit as compared to the delay related to the feedback path may cause such a hazard.

Essential hazards can’t be corrected by adding redundant gates as in static hazards.

The problem that they impose is often corrected by adjusting the quantity of delay within the affected path.

To avoid essential hazards, each feedback circuit must be handled with individual care to make sure that the delay within the feedback path is long enough compared with delays of other signals that originate from the input terminals.

Also Read:

  1. Digital To Analog Converters
  2. Analog To Digital Converters
  3. Logic Gates and Its Truth Table
  4. Classification of Logic Families
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