Data Transfer Instructions In 8085

There are 5 types of instruction sets available in the 8085 microprocessor. Today we are going to learn about the data transfer instructions in 8085 microprocessor.

Data transfer instructions in 8085 microprocessors are used to move data between processor registers, memory, and I/O devices.

Data transfer instructions copied data from source to destination without modifying the contents of the source.

The various types of data transfer that are possible between direct data, registers, and memory locations are as follows:

Sr. No	Data Transfer	Example
1.	Between registers	Register B -> Register D
2.	Specific data byte to register or a memory location	Data Byte -> Register B
3.	Between memory location and register	Memory Location -> Register A
4.	Between the I/O device and the accumulator	Input Device -> Register A
5.	Between a register pair and the stack	Register Pair data -> Stack Location

Data Transfer Instructions In 8085

The data transfer instructions in 8085 include the following instructions:

1.	MOV Rd, Rs	2.	MOV R, M	3.	MOV M, R
4.	MVI R, data	5.	MVI M, data	6.	LXI Rp, 16-bit data
7.	LDA address	8.	STA address	9.	LHLD address
10.	SHLD address	11.	LDAX Rp	12.	STAX Rp
13.	XCHG

Now, we will see each instruction which we have to describe above table in detail.

MOV R_d, R_s

Description	This instruction copies data from the source register Rd to the destination register Rs. The source register Rd and destination register Rs can be any general-purpose register like A, B, C, D, E, H, or L. The contents of the source register remain unchanged.
Example MOV C, M	This instruction will copy the contents of register C to register B. The contents of register C remain unchanged. Example MOV B, C Suppose B = 20H, C = 10H, and the instruction MOV B, C is executed. After the execution B 10H and C= 10H.

Machine Cycle Details:

1. Opcode Fetch: For this cycle the address given by the program counter. The program counter places the address on the lower order address bus and the higher order address bus. The program counter is incremented by one to point to the next instruction.

MOV R, M

Description

This instruction copied data from memory M to register R. The term M specifies the HL memory pointer. The contents of the HL register pair are used as the address of the memory location. The contents of that memory location are transferred to the specified register R. The register R can be any general-purpose register like A, B, C, D, E, H, or L.

Example MOV C, M

This instruction will copy the data from the memory location pointed by the HL pair to the C register. Let the contents of the HL register pair be F000H, register C = 20H. At the address F000H: 10H is stored. The HL register pair contents are used as the address i.e HL= F000H. The contents of memory location F000H are copied to register C. So the content of the C register will change from 20H to 10H. The contents of the memory location remain unchanged.

Machine Cycle Details:

1. Opcode Fetch: The program counter places the address on the higher order and lower order address bus. This cycle fetches OPCODE from program memory using a PC. The opcode is read into the microprocessor and is decided. 4T states are required for the completion of this operation. The PC is then incremented by 1 to point to the next instruction.
2. Memory Read: The address will be specified by the HL register pair. The data present at the memory location pointed by the HL register pair is read into the register specified. The PC is then incremented by one and points to the next instruction.

The example of instruction MOV R, M are:

MOV A, M	MOV B, M	MOV C, M	MOV D, M
MOV E, M	MOV L, M	MOV H, M

Note:

1. Whenever the term M comes in an instruction, it is a memory pointer. The address will be given by the HL register pair.
2. Brackets around HL specify that the contents are used as an address. Henceforth the brackets will be used to specify the contents used ad address.

MOV M, R

Description	This instruction copied data from register R to memory M. The term M specifies the HL memory pointer. The contents of the specified register are copied to that memory location pointed by the HL register pair. The register R can be any general-purpose register like A, B, C, D, E, H, or L. The contents of the memory location remain unchanged.
Example MOV M, C	Let the contents of the HL pair be E200H, register C = 20H, at address E200: 10H is stored. On the instruction MOV M, C the data is transferred from the C register to memory. The contents of register C are copied to memory location E200H, so the contents of memory location C200H will change from 10H to 20H.

Machine Cycle Details:

1. Opcode fetch: The program counter places the address on the higher order and lower order address bus. The opcode at this memory location is read into the microprocessor. The PC is then incremented by 1 to point to the next instruction. This machine cycle required 4T states.
2. Memory Write: This machine cycle is required for writing the data from the specified register to a memory location that is specified by the HL register pair.

Other examples of the instruction MOV M, R is:

MOV M, A	MOV M, B	MOV M, C	MOV M, D
MOV M, E	MOV M, L	MOV M, H

MVI R, Data

Description	This instruction moves the 8-bit immediate data to the specified register. The data is specified within the instruction. It is a two-byte instruction, so the first byte of instruction will be OPCODE, and the second byte will be 8-bit data. The register R can be any general-purpose register like A, B, C, D, E, H, or L.
Example MVI D, 07H	This instruction will load the immediate data 07H in register D. Let the contents of register D = 10H. Then after execution of instruction MVI D, 07H the content of register D will be changed from 10H to 07H.

Machine Cycle Details:

1. Opcode fetch: The program counter places the address on the higher order and the lower order address bus. The opcode at this memory location is read into the microprocessor. The PC is then incremented by 1 to point to the next byte. The machine cycles required 4T states.
2. Memory Read: The data is read from the addressed memory location into the specified register. The PC is again incremented by one to point to the next instruction after MVI.

The example of instruction MVI R, data are:

MVI A, data	MVI B, data	MVI C, data	MVI D, data
MVI E, data	MVI L, data	MVI H, data

MVI M, data

Description	This instruction moves immediate data to memory. The HL register pair is used as a memory pointer. The contents of the HL register pair are used as memory addresses and the immediate data is transferred to that memory location.
Example MVI H, 10H MVI L, 00H MVI M, 20H	10H is transferred to the H register. 00H is transferred to the L register. 20H is transferred to memory. When the instruction MVI M, 20H is executed, the data 20H will be stored in the memory location addressed by the HL register pair. i.e 1000H.

Machine Cycle Details:

1. Opcode Fetch: The program counter places the address on the higher order and the lower order address bus. The opcode at this memory location is read into the microprocessor. The PC is then incremented by 1 to point to the next byte. This machine cycle requires 4T states.
2. Memory Read: The program counter places the address on the lower and higher order address bus. The data given within the instruction is read. PC is then incremented by one and points to the next instruction.
3. Memory Write: HL contents will appear on the address bus. The contents of the H register are higher order byte of the address and the contents of the L register are the lower order byte of the address. \overline{WR} signal is generated to perform a write operation in data memory.

LXI R_p, 16-bit Data

Description

This instruction will load the register pair with 16-bit data. This instruction loads 16-bit data specified within the instruction to the specific register pair or stack pointer. In the instruction, only high order register is specified for the register pair. I.e if the HL pair is to be loaded only the H register will be specified in the instruction. The register pair Rp can be BC, DE, HL register pairs, or the stack pointer SP.

Example LXI H, 2030H LXI SP, 7FFFH

Load HL pair with 2030H. 20H will be loaded in the H register and 30H in the L register. The instruction will load stack pointer SP with 7FFFH.

Machine Cycle Details:

1. Opcode Fetch: The program counter places the address bus on the higher order and the lower order address bus. This cycle will fetch opcode from program memory using the PC. The PC is then incremented by 1 to point to the next byte.
2. Memory Read: The program counter places the address on the lower order address bus and the higher order address bus. The lower order byte is read using PC into the lower order byte of the specified register pair. The PC is then incremented by one to point next byte.
3. Memory Read: The program counter retains the addresson the lower order address bud and the higher order address bus. The higher order byte is read using PC into the higher order byte of the specified register pair. The PC is then incremented by one to point to the next instruction.

The example of the instruction LXI R_p, 16-bit data are:

LXI B, 16-bit data	LXI D, 16-bit data
LXI H, 16-bit data	LXI SP, 16-bit data

LDA Address

Description	Load accumulator direct from memory. This instruction copies the contents of the memory location whose address is specified in the instruction to the accumulator. The contents of the memory location remain unchanged.
Example LDA 5820H	This instruction will load the accumulator with the contents of memory location 5820H. Let initially A = F0H, contents of memory location 5820H = 15H. Then after the execution of instruction LDA 5820H, the accumulator will be loaded with 15H. The content of the accumulator will change from F0H to 15H.

Machine Cycle Details:

1. Opcode Fetch: The program counter places the address on the higher order and the lower order address bus. This cycle will fetch Opcode from program memory using a PC. The PC is then incremented by 1 to point to the next byte.
2. Memory Read: The program counter places the address on the lower order address bus and the higher order address bus. The lower-order byte of the address specified is read using a PC. The PC is then incremented by one to point to the next byte.
3. Memory Read: The program counter places the address on the lower order address bus and the higher order address bus. The higher-order byte of the address is read using a PC. The PC is then incremented by one to point to the next instruction.
4. Memory Read: This machine cycle is used for reading the data into the accumulator from the addressed memory location. The address for this is given by the above 2 memory read cycles that have taken the higher and lower order address.

STA Address

Description	Store accumulator direct to memory. his instruction will store the contents of the accumulator to the memory location specified in the instruction. The contents of the memory location remain unchanged. It is a 3-byte instruction. The first byte is the opcode, the second byte is the lower-order address and the third byte is the higher-order address.
Example LDA 5820H	This instruction will store the contents of the accumulator at location 5820H.

Machine Cycle Details:

1. OPCODE fetch: The program counter places the address on the higher order and the lower order address bus. This cycle will fetch OPCODE from program memory using a PC. The PC is then incremented by 1 to point to the next byte. The opcode of this instruction is 32 H.
2. Memory read: The program counter places the address on the lower order address bus and the higher order address bus. The lower-order byte of the address specified is read using a PC. The PC is then incremented by one to point to the next byte.
3. Memory read: The program counter retains the address on the lower order address bus and the higher order address bus. The higher-order byte of the address is read using a PC. The PC is then incremented by one to point to the next instruction.
4. Memory write: This machine cycle is used for writing the data from the accumulator to the addressed memory location. The address for this is given by the above 2 memory read cycles that have taken the higher and lower order address.

LHLD Address

Description

Load HL pairs directly from memory. This instruction loads the contents of the memory location to the H and L registers. The address of memory is specified along with the instruction. The contents of the memory location whose address is specified in the instruction are transferred to the L register and the contents of the next memory location i.e. (address + 1) to the H register. This instruction is used to load the H and L registers from memory. It is a 3-byte instruction. The first byte is the opcode, the second byte is the lower-order address and the third byte is the higher-order address.

Example LHLD 4000H

Load HL pair from memory locations 4000H and 4001H. Let H = 05 H, L = 04 H, at memory locations 4000 H and 4001 H the data 20H, 30H is stored. The instruction LHLD will load the contents of memory location 4000 H to the L register, and the contents of memory location 4001 H to the H register. So the contents of register L will change from 04 to 20 H and the contents of register H will change from 05 H to 30 H.

Machine Cycle Details:

1. OPCODE fetch: The program counter places the address on the lower order address bus and the higher order address bus. This cycle is used to read the OPCODE of LHLD instruction. The opcode of the LHLD instruction is 2A H. The address for this machine cycle is given by PC. The PC is then incremented by 1 to point to the next byte.
2. Memory read: The program counter places the address on the lower order address bus and the higher order address bus. The lower-order byte of the address specified is read using a PC. The PC is then incremented by one to point to the next byte.
3. Memory read: The program counter retains the address on the lower order address bus and the higher order address bus. The higher-order byte of the address is read using a PC. The PC is then incremented by one to point to the next instruction.
4. Memory read: It is used to read data from the addressed memory. This data will be stored in the L register. The address for this is given by the above 2 memory reads. This address will be incremented by 1.
5. Memory read: It is used to read data from addressed memory. This data will be stored in the H register.

SHLD Address

Description	Store HL pair to memory locations 4000 and 4001. Let H = 05H, L = 04H, at memory locations 4000H and 4001H the data 20H and 30H is stored and the instruction SHLD 4000H has executed the contents of register L are copied to memory location 4000H and contents of register H are copied to memory location 4001H.
Example SHLD 4000H	Store HL pair to memory locations 4000 and 4001. Let H = 05H, L = 04H, at memory locations 4000H and 4001H the data 20H and 30H is stored and the instruction SHLD 4000H has executed the contents of register L are copied to memory location 4000H and contents of register H are copied memory location 4001H.

Machine Cycle Details:

1. OPCODE fetch: The program counter places the address on the lower order address bus and the higher order address bus. This cycle is used to read the OPCODE of SHLD instruction. The opcode of the SHLD instruction is 22 H. The address for this machine cycle is given by PC. The PC is then incremented by 1 to point to the next byte.
2. Memory read: The program counter places the address on the lower order address bus and the higher order address bus. The lower-order byte of the address specified is read using a PC. The PC is then incremented by one to point to the next byte.
3. Memory read: The program counter retains the address on the lower order address bus and the higher order address bus. The higher-order byte of the address is read using a PC. The PC is then incremented by one to point to the next instruction.
4. Memory write: It is used to write data i.e. contents of the L register to the addressed memory. The address for this is given by the above 2 memory reads. This address will be incremented by 1.
5. Memory write: It is used to write data in the H register to address the memory. This data will be stored at the memory location with incremented address.

LDAX R_p

Description	Load accumulator indirectly by using a memory pointer. This instruction copies the contents of the memory location to the accumulator. The address of memory location is given by R, register pair specified along with the instruction. The register pair Rp can be BC or DE only. The contents of the memory location remain unchanged.
Example LDAX B	This instruction will load the accumulator with the contents of the memory location whose address is given by the BC register pair. Let A = 1F H, B = 20H, C = 25H, at memory location 2025 : 56H is stored. Then after the execution of instruction LDAX B, the accumulator will be loaded with the contents of memory location 2025 i.e. 56 H.

Machine Cycle Details:

1. OPCODE fetch: The program counter places the address on the higher order and the lower order address bus. This cycle will fetch OPCODE (e.g. 0A H for LDAX B) from program memory using PC. The PC is then incremented by 1 to point to the next instruction.
2. Memory read: The address will be specified by the register pair. The data present at the memory location pointed by the specified register pair is read into the accumulator. In this machine cycle the higher order register contents are placed on the higher order address bus and lower order register contents are placed on the lower order address bus.

The example of instruction LDAX R_p are:

1. LDAX B

2. LDAX D

STAX R_p

Description	Store accumulator indirectly by using a memory pointer. This instruction copies the contents of the accumulator to memory location. The address of the memory location is given by the Rp register pair specified in the instruction. The register pair Rp can be a valid register pair like BC or DE only. The contents of the accumulator remain unchanged.
Example STAX B	Store accumulator indirectly by using a memory pointer. This instruction copies the contents of the accumulator to the memory location. The address of the memory location is given by the Rp register pair specified in the instruction. The register pair Rp can be a valid register pair like BC or DE only. The contents of the accumulator remain unchanged.

Machine Cycle Details:

1. OPCODE fetch: The program counter places the address on the higher order and the lower order address bus. This cycle will fetch OPCODE from program memory using a PC. The PC is then incremented by 1 to point to the next instruction.
2. Memory write: Higher order address is obtained from higher order register and lower order address is obtained from lower order register. The contents of the accumulator are stored in the addressed memory location. Thus, this machine cycle is required for writing the data from the accumulator to the memory location that is pointed by the specified register pair.

The example of instruction LDAX R_p are:

1. STAX B

2. STAX D

XCHG

Description	Exchange the contents of HL with DE pair. This instruction exchanges the contents of the H register with the D register and the L register with the E register.
Example XCHG	Let H = 12H, L = 11H, D = 30H, E executed. 40H and the instruction XCHG is executed.

Machine Cycle Details:

1. OPCODE fetch: For this cycle, the address is given by the program counter. The program address counterlaces the lower order on the address bus and the higher order address bus. The program counter is incremented by one, to point to the next instruction.

Data Transfer Instruction 8085 Programs

1. Write a program to load the data into the accumulator and any register.

2. Write a program to exchange the contents of memory locations.

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