Introduction
In a microprocessor Based system, we come across two important modes, i.e timer -> to provide delay and counter -> to count incoming pulses. Presently, the way we implement timer/counter in 8085 based system has the following drawbacks:
- Delay: The 8085 can provide delays of any value, but it uses software to implemet the delay. The instruction are arranged to waste time. The main disadvantage of this scheme is 8085 is executing some instructions, it means that it is busy in doing work.
- Counter: The 8085 can count number of pulses arriving at port. To implement this 8085 goes on checking port, if it is actuve it increasing counter by 1 and again goes on checking port. The same disadvantage, 8085 will have to execute instructions.
In a large system, where 8085 wastage time is critical, a separate time IC 8254 can be used. 8254 programmable interval timer consists of 3 identical 16-bit counters. These counters can work as counters or can provide accurate time delays. To operate as a counter, a 16-bit count is loaded and the desired mode of operation is selected. The counters will work independently and generate the desired output. Now the 8085 Microprocessor job is to initialize and load counters.
Difference between 8253 and 8254 programmable Interval Timer
| 8253 | 8254 |
|---|---|
| Operating frequency 0 – 2.6 MHz | Operating frequency 0 – 10 MHz |
| Uses N-MOS technology | Uses H-MOS technology |
| Read-Back command is not available. | Read-Back command is available. |
| Read and writes of the same counter cannot be interleaved. | Reads and writes of the same counter can be interleaved. |
Features of 8254 Prgrammable Interval Timer
- Three independent 16 bit down counters.
- Counters can be programmed in 6 different programmable counter modes.
- Counting facility in both binary or BCD number system.
- Compatible with Intel and other microprocessor.
- Single +5 V supply.
- 24 Pin dual in-line package.
- It is completely TTL compatible.
- It has powerful command called READ BACK COMMAND which allows the user to check the count value, programmed mode and current mode and the current status of the counter.
- Operating frequency range; FOr 8253 -DC to 2.6 MHz; For 8254 – DC to 10 MHz.
Block Diagram of 8254 Programmable Interval Timer
The block diagram of 8254 Programmable Interval Times is as shown in the figure below:
It includes a data bus buffer, read/write logic, control word register, and counters.
1. Dats Bus Buffer:
- It is tristate, bidirectional 8 bit data bus buffer.
- It is used to interface 8254 data bus with system data bus.
- It is internally connected to internal data bus and its outer pins D0-D7 are connected to system data bus. The direction of data buffer is decided by read and write control signals.
2. Read/Write Logic:
- Thic block accepts inputs from system control bus and address bus.
- In I/O mapped I/O, the signals \overline{RD} and \overline{WR} are connected to \overline{IOR} and \overline{IOW}.
- In memory mapped I/O \overline{RD} and \overline{WR}, are connected to \overline{MEMR} and \overline{MEMW}.
- A0 and A1 are direcly connected to address lines A0 and A1.
- \overline{CS} is connected to address decoder.
- The 8254 operation/selection is enables/disabled by \overline{CS} signal. A0, A1 selects a specifi part \overline{WR}, \overline{RD}decides writing data to 8254 or reading data from 8254.
- The control word registers and the counters are selected accoring to the signals on line A0 and A1.
| A1 | A0 | Selection |
|---|---|---|
| 0 | 0 | Counter 0 |
| 0 | 1 | Counter 1 |
| 1 | 0 | Counter 2 |
| 1 | 1 | Control word register |
3. Control Word Register:
- This register of 8254 programmable interval timer gets selected when A0=1 and A1=1.
- It is used to specify the BCD or binary counter to be used, its mode of operation and the data transfer to be used i.e read or write the data bytes.
- If the CPU performs a write operation, the data is stored in the control word register and is preffered to as control word. It is used to define counter operation.
- The data can only be written into control word register, no read operation is allowed. Status inforamtion is available with the help of read back command.
4. Counters:
- There are three independent, 16-bit down counters.
- They can be programmed separately through control word register to decide mode of counter.
- Each counter is having 2 inputs viz. CLK and GATE.
- CLK is used as an input to counnter and GATE is used to control the counter.
- The counters give output on OUT pin.
- The loaded count value in counter will be decremented by counter at each clock input pulse. The programmer can read counter without disturbing counter operation.
Pin Configuration of 8254 Programmable Interval Timer
The pin configuration of Pin Configuration of 8254 Programmable Interval Timer is as shown in the figure below:
| D7 – D0 | I/O | Data Bus |
| CLKN | I | Counter Inputs |
| GATEN | I | Counter GATE inputs |
| OUTN | O | Counter outputs |
| \overline{RD} | I | Read |
| \overline{WR} | I | Write |
| \overline{CS} | I | Chip Select |
| A0 – A1 | I | Counter select |
| VCC/GND | I | +5 V supply/Ground |
Pin Description:
| Symbol | Name | Function |
|---|---|---|
| D7 – D0 | Data Bus | These are 8-bit bidirectional data bus lines, connected to the system data bus for data transfer between 8085 and 8254. |
| \overline{CS} | Chip Select | This is an active low input signal, used to select the 8254 IC. If \overline{CS} = 0 then 8254 will be active and take part in data transfer from/to 8085 otherwise 8254 will be in de-active state. |
| \overline{RD} | Read | This is an active low input signal, used in coordination with A0, A1 to send data from appropriate counter to data lines D7 – D0. |
| \overline{RD} | Write | This is an active low input signal, used in coordination with A0, A1 to load counters or to initialize counters. |
| A0 – A1 | Address Lines | These are input address lines used to distinguish different parts of 8254 such as counter 0, counter1, counter 2, control word register. |
| CLK0-2 | Clock Input | These are clock inputs to 3 independent counters. The pulse applied at these pins will be counted by the respective counter. |
| GATE0-2 | Gate Control | These are active high, input signals used to allow external hardware to control the respective counter. The function of gate input is dependent on the operating mode. |
| OUT0-2 | Output | These Lines are active high, output lines. The output is dependent on operating modes. |
Control Word Register Formate of 8254
The control word register formate of 8254 programmable interval timer is as shown in the figure below:
- The control word register bits, SC1 and SC0, select the control word register for counter and used to initialize the counters.
- A0 and A1 selects counters, but they used to read/load counters by microprocessor.
- The bits RL0 and RL1 are used to read/load, data bytes i.e LSB byte, MSB byte or both LSB and MSB bytes.
- The bits M2, M1 and M0 decides the mode of operation for selected counter, Mode0- Mode5.
- The bit, BCD, decides the mode of counting i.e BCD counter or binary counter.
Operating Modes of 8254 Programmable Interval Timer
The 8254 programmable interval timer IC provides the following modes of operation of 8254:
- Mode 0 : Interrupt on Terminal Count
- Mode 1 : Programmable One Shot/ Hardware Triggerable One Shot
- Mode 2 : Rate Generator / Pulse Generator
- Mode 3 : Square Wave Generator
- Mode 4 : Software Triggered Strobe
- Mode 5 : Hardware Triggered Strobe
