Microprocessor

8259A Programmable Interrupt Controller

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For applications where we require multiple interrupt sources, we need to use am external devices called a programmable interrupt controller (PIC).

By connecting PIC to the microprocessor we can increase the interrupt handling capacity of the microprocessor.

8259A programmable interrupt controller is the commonly used priority interrupt controller.

Table of Contents

Features of 8259 PIC

It is a LSI chip which manages 8 levels of nterrupts i.e. it is used to impelement 8 level interrupt system.
It can be cascaded in a master slave configuration to handle upto 64 levels of interupts.
It can identify the interrupting device.
It can resolve the priority of interrupt request i.e. it does not require any exter
It can be operated in various priority modes such as fixed priority and rotating priority.
The interrupt requests are individually maskable.
It providees 8 bit vector number as an interrupt information.
It does not require clock signal.
It can be used in polled as well as interrupt modes.
The starting address of vector number is programmable.
It can be used in buffered mode. (Buffered mode is applicable for multiprocessor system).

Block Diagram of 8259A Programmable Interrupt Controller

The block diagram of 8259 is as shown in the figure below. It contains the following blocks:

Data Bus Buffer
Cascade buffer and comparator
IRR (Interrupt Request Register)
Priority resolver

Read/write logic
Control Logic
InSR (In-service Register)
IMR (Interrupt Mask Register)

(1) Data Bus Buffer: It is used to transfer data between the microprocessor and internal bus.

(2) Read/Write control logic: It sets the direction of the data bus buffer. It controls all internal read/write operations. It contains initialization and operation command registers.

(3) Cascaded buffer and comparator: In master mode, it functions as a cascaded buffer. The cascaded buffer outputs slave identification number on cascade lines. In slave mode, it functions as a comparator. The comparator reads slave identification numbers from cascade lines and compares this number with its internal identification number. In buffered mode, it generates an EN signal.

(4) Control Logic: It generates an INT signal. In response to the INTA signal, it releases a three-byte CALL address or a one-byte vector number. It controls read/write control logic, cascade buffer/comparator, in-service register, priority resolver, and IRR.

(5) Interrupt request register (IRR): It is used to store all pending interrupt requests. Each bit of this register s set at the rising edge or at the high level of the corresponding interrupt request line. The microprocessor can read the contents of this register by issuing appropriate command words.

(6) In-service register (InRR): It is used to store all interrupt levels currently being serviced. Each bit of this register is set by priority resolver and reset by End of the interrupt command word. The microprocessor can read the contents of this register by issuing appropriate command words.

(7) Priority resolver: It determines the priorities of the bit set in the IRR. To make a decision, the priority resolver looks at the ISR. If the higher priority bit in the InSR is set then it ignores the new request. If the priority resolver finds that the new interrupt has a higher priority than the highest priority interrupts currently being serviced and the new interrupt is not in service, then it will set the appropriate bit in the InSR and send the INT signal to the interrupt request.

(8) Interrupt mask register (IMR): It is a programmable register. It is used to mask unwanted interrupt requests, by writing appropriate command words. The microprocessor can read the contents of this register without issuing any command word.

Pin Configuration of 8259A Programmable Interrupt Controller

The pin configuration of 8259 PIC (Programmable Interrupt Controller) is as shown in the figure below:

D₀-D₇	I/O	Data Bus
$\overline{RD}$	I	I/O read
$\overline{WR}$	I	I/O write
$\overline{CS}$	I	Chip select
INT	O	Interrupt request ( To 8085)
$\overline{INTA}$	I	Interrupt acknowledge (From 8085)
A₀	I	Address line
IR₀-IR₇	I	Interrupt request ( To 8085)
$\overline{SP}$ / $\overline{EN}$	I/O	Slave program / Enable buffer
CAS0-CAS2	I/O	Cascade lines

Symbol	Description
D₀-D₇	These are b-directional, tristate, buffered, non multiplexed data lines. These lines are connected to the system data lines directly or through data buffers.
$\overline{RD}$	It is an active low control input line. It is used to read contents of the internal registers. it is connected to $\overline{IOR}$ or $\overline{MEMR}$ of the system bus.
$\overline{WR}$	It is an active low control input line. It is used to write data into registers. it is connected to $\overline{IOWR}$ or $\overline{MEMWR}$ of the system bus.
A₀	It is an address input line. it is used to select the appropriate control register. It is connected to one of the address lines of the system address bus.
$\overline{CS}$	It is an active low chip select input line. it is used to select 8259 A chip. This signal is generated by the address decoder.
CAS0-CAS2	These are bi-directional 3-bit cascade lines. These lines are used in cascade mode only. In master mode, these lines function as output lines. In this mode, the pIC places a 3-bit slave identification number on cascade lines.
$\overline{SP}$ / $\overline{EN}$	It is an active low bi-directional control line. In non buffered mode, it functions as $\overline{SP}$ input line. In this mode, $\overline{SP}$ is used to distinguish between master and slave PICs. In buffered mode it functions as an $\overline{EN}$ output line. In this mode, it is used to enable data buffers.
INT	It is an interrupt output line. it goes high whenever a valid interrupt request is activated. It must be connected to the INTR input of the microprocessor.
$\overline{INTA}$	It is an interrupt acknowledge input line. This signal is generated by the microprocessor. The 8259A accepts two $\overline{INTA}$ pulses to release one-byte vector number. The 8259 A does not work without $\overline{INTA}$ pulses in vectored mode.
IR₀-IR₇	These are asynchronous interrupt request input lines. These signals are generated by peripherals. They can be used whether in edge-triggered or level-triggered mode. The IR input should make low to high transition n level as well as edge-triggered mode.

Pin configuration of 8259 PIC

Priority Modes of 8259A Programmable Interrupt Controller

The various priority modes of 8259A are:

Fully nested mode
Special fully nested mode
Rorating Priority mode
- The rotating priority mode can be set as:
  1. Automatic rotation
  2. Specifc rotation
Special masked Mode

Operating Modes of 8259A Programmable Interrupt Controller

8259 has two operating modes:

Interruput drive: In this mode, 8259 Interrrupts the processir with the INT pin wheneve it gets an interupt.
Polled Mode: In this mode, the INT output is not used. The microprocessor checks the status of the interrupt request by issuing poll command.