8259A Programmable Interrupt Controller

For applications where we require multiple interrupt sources, we need to use external devices called programmable interrupt controllers (PIC).

By connecting PIC to the microprocessor we can increase the interrupt handling capacity of the microprocessor. 8259A programmable interrupt controller is the commonly used priority interrupt controller.

Table of Contents

Features of 8259 PIC

It is an LSI chip that manages 8 levels of interrupts i.e. it is used to implement 8 level interrupt system.
It can be cascaded in a master-slave configuration to handle up to 64 levels of interrupts.
It can identify the interrupting device.
It can resolve the priority of interrupt requests i.e. it does not require any extra
It can be operated in various priority modes such as fixed priority and rotating priority.
The interrupt requests are individually maskable.
It provides an 8-bit vector number as interrupt information.
It does not require a clock signal.
It can be used in polled as well as interrupt modes.
The starting address of the vector number is programmable.
It can be used in buffered mode. (Buffered mode is applicable for multiprocessor systems).

Also Read: 8237 DMA Controller

Block Diagram of 8259A Programmable Interrupt Controller

The block diagram of 8259 is shown in the figure below. It contains the following blocks:

Data Bus Buffer
Cascade buffer and comparator
IRR (Interrupt Request Register)
Priority resolver

Read/write logic
Control Logic
InSR (In-service Register)
IMR (Interrupt Mask Register)

(1) Data Bus Buffer: It is used to transfer data between the microprocessor and internal bus.

(2) Read/Write control logic: It sets the direction of the data bus buffer. It controls all internal read/write operations. It contains initialization and operation command registers.

(3) Cascaded buffer and comparator: In master mode, it functions as a cascaded buffer. The cascaded buffer outputs a slave identification number on cascade lines. In slave mode, it functions as a comparator. The comparator reads slave identification numbers from cascade lines and compares this number with its internal identification number. In buffered mode, it generates an EN signal.

(4) Control Logic: It generates an INT signal. In response to the INTA signal, it releases a three-byte CALL address or a one-byte vector number. It controls read/write control logic, cascade buffer/comparator, in-service register, priority resolver, and IRR.

(5) Interrupt request register (IRR): It is used to store all pending interrupt requests. Each bit of this register s set at the rising edge or at the high level of the corresponding interrupt request line. The microprocessor can read the contents of this register by issuing appropriate command words.

(6) In-service register (InRR): It is used to store all interrupt levels currently being serviced. Each bit of this register is set by the priority resolver and reset by the End of the interrupt command word. The microprocessor can read the contents of this register by issuing appropriate command words.

(7) Priority resolver: It determines the priorities of the bit set in the IRR. To make a decision, the priority resolver looks at the ISR. If the higher priority bit in the InSR is set then it ignores the new request. If the priority resolver finds that the new interrupt has a higher priority than the highest priority interrupts currently being serviced and the new interrupt is not in service, then it will set the appropriate bit in the InSR and send the INT signal to the interrupt request.

(8) Interrupt mask register (IMR): It is a programmable register. It is used to mask unwanted interrupt requests, by writing appropriate command words. The microprocessor can read the contents of this register without issuing any command word.

Also Read: 8254 programmable interval timer

Pin Configuration of 8259A Programmable Interrupt Controller

The pin configuration of 8259 PIC (Programmable Interrupt Controller) is as shown in the figure below:

D₀-D₇	I/O	Data Bus
$\overline{RD}$	I	I/O read
$\overline{WR}$	I	I/O write
$\overline{CS}$	I	Chip select
INT	O	Interrupt request ( To 8085)
$\overline{INTA}$	I	Interrupt acknowledge (From 8085)
A₀	I	Address line
IR₀-IR₇	I	Interrupt request ( To 8085)
$\overline{SP}$ / $\overline{EN}$	I/O	Slave program / Enable buffer
CAS0-CAS2	I/O	Cascade lines

Symbol	Description
D₀-D₇	It is an active low-control input line. It is used to write data into registers. it is connected to $\overline{IOWR}$ or $\overline{MEMWR}$ of the system bus.
$\overline{RD}$	It is an active low-control input line. It is used to read the contents of the internal registers. It is connected to $\overline{IOR}$ or $\overline{MEMR}$ of the system bus.
$\overline{WR}$	It is an interrupt acknowledge input line. This signal is generated by the microprocessor. The 8259A accepts two $\overline{INTA}$ pulses to release a one-byte vector number. The 8259 A does not work without $\overline{INTA}$ pulses in vectored mode.
A₀	It is an address input line. it is used to select the appropriate control register. It is connected to one of the address lines of the system address bus.
$\overline{CS}$	It is an active low-chip select input line. it is used to select the 8259 A chip. This signal is generated by the address decoder.
CAS0-CAS2	These are bi-directional 3-bit cascade lines. These lines are used in cascade mode only. In master mode, these lines function as output lines. In this mode, the pIC places a 3-bit slave identification number on cascade lines.
$\overline{SP}$ / $\overline{EN}$	It is an active low bi-directional control line. In nonbuffered mode, it functions as $\overline{SP}$ input line. In this mode, $\overline{SP}$ is used to distinguish between master and slave PICs. In buffered mode, it functions as an $\overline{EN}$ output line. In this mode, it is used to enable data buffers.
INT	It is an interrupt output line. it goes high whenever a valid interrupt request is activated. It must be connected to the INTR input of the microprocessor.
$\overline{INTA}$	It is an interrupt acknowledge input line. This signal is generated by the microprocessor. The 8259A accepts two $\overline{INTA}$ pulses to release a one-byte vector number. The 8259 A does not work without $\overline{INTA}$ pulses in vectored mode.
IR₀-IR₇	These are asynchronous interrupt request input lines. These signals are generated by peripherals. They can be used whether in edge-triggered or level-triggered mode. The IR input should make low to high transition n level as well as edge-triggered mode.

Pin configuration of 8259 PIC

Also Read: 8255 PPI (Programmable Peripheral Interface)

Priority Modes of 8259A Programmable Interrupt Controller

The various priority modes of 8259A are:

Fully nested mode
Special fully nested mode
Rorating Priority mode
- The rotating priority mode can be set as:
  1. Automatic rotation
  2. Specific rotation
Special masked Mode

Operating Modes of 8259A Programmable Interrupt Controller

8259 has two operating modes:

Interrupt drive: In this mode, 8259 Interrupts the processor with the INT pin whenever it gets an interrupt.
Polled Mode: In this mode, the INT output is not used. The microprocessor checks the status of the interrupt request by issuing the poll command.

FAQs on 8259A Programmable Interrupt Controller

What is an 8259A Programmable Interrupt Controller?

The programmable interrupt controller 8259A is a device used in computer systems to manage interrupt requests from different devices. It receives interrupt requests from various devices, prioritizes them, and sends them to the CPU for processing.

What is the difference between 8259 and 8259A?

The 8259 is the original version of the programmable interrupt controller, while the 8259A is an improved version with additional features such as automatic end of interrupt (EOI) and edge/level triggering modes.

What is the control word format of 8259?

The control word format of 8259 is an 8-bit command word that consists of three fields: the operation code, the interrupt level, and the mode.

What is used to select the 8259A Programmable Interrupt Controller?

The chip select (CS) pin is used to select the 8259A chip. When the CS pin is low, the chip is selected and ready to receive commands.

What is the interrupt controller?

An interrupt controller is a hardware device that manages interrupts generated by various devices in a computer system. It receives interrupt requests, prioritizes them, and sends them to the CPU for processing. The interrupt controller helps to improve the performance of the system by allowing the CPU to handle interrupts from different devices in an organized manner.

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