8255 PPI (Programmable Peripheral Interface)

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Introduction

  • The 8255 PPI is a programmable peripheral interface device.
  • It is a general purpose programmable parallel I/O device.
  • It contains 3 I/O ports which can be programmed in different modes.
  • To program the function to all three i/O ports t contains a register called as control registers. The control register defines the function of each I/O port and in which mode they sould operate.
  • 8055 PPI is a general puspose in nature and provides many facilities for connecting different devices. So it is used frequently in different applications.

Features of 8255 PPI

  • It is a progammable parallel I/O device.
  • It contains 24 programmable I/O pins arranged as 2-8 bit ports and 2-4 bit ports.
  • It has 3, 8-bit ports: Port A, Port B and Port C, which are arranged in two group of 12 pins.
  • Fully compatible with Intel microprocessor families.
  • TTL compatible.
  • Direct bit set/reset capability is available for port C.
  • Improved DC driving capability.
  • It can operate in 3 Modes:
    1. Mode 0 : Simple I/O
    2. Mode 1 : Strobed I/O
    3. Mode 2 : Strobed bi-directional I/O

Pin Configuration of 8255 PPI

The pin configuration of 8255 PPI (Programmable Peripheral Interface) is as shown in the figure below:

8255 PPI pin configuration

PA0-PA7I/OPort A pins
PB0-PB7I/OPort B pins
PC0-PC7I/OPost C pins
D0-D7I/OData pins
RESETIReset input
\overline{RD}IRead input
\overline{WR} I Write input
A0-A1IAddress pins
\overline{CS} IChip select
VCC-GNDI+5 V supply ground
SymbolNameFunction
D0-D7 Data BusThese are 8-bit bi-directional data bus lines, connected to the system data bus for data transfer between CPU and 8255.
\overline{CS} Chip selectThis is an active LOW input signal used to select 8255 IC. If \overline{CS} = 0 then 8255 will get selected and take part in data transfer from/to CPU, otherwise 255 will be in inactive state.
\overline{RD} ReadThis is an active low input signal used in coordination with another signal to send data to the CPU through data lines.
\overline{WR} Wite This is an active low input signal used in coordination with another signal to send data to 8255.
A0-A1 Address linesThese are input, active HIGH address lines used to distinguish different ports of 8255 such as Port A, Port B, Port C, Control register.
RESET ResetThis is an active HIGH input signal used to reset 8255. When 8255 is reset, it clears the control word register and all ports are set to input mode.
PA0-PA7 Port A pins 0 to 7These are 8-bit bidirectional I/O pins used to send data to the peripheral or to read data from the peripheral. The contents are transferred to/from Port A.
PB0-PB7 Port B pins 0 to 7 These are 8-bit bidirectional I/O pins used the same as PA0-PA7
PC0-PC7 Port C pins 0 to 7 These are 8-bit bidirectional I/O pins. These lines are divided into 2 sections i.e. PC0-PC3 and PC4-PC7. These two sections can be individually used to transfer 4 bits of data from two separate port C sections.

8255 PPI Functional Block Diagram

The block diagram of 8255 PPI is as shown in the figure below:

It contains the following blocks

  1. Data bus buffer
  2. Read/Write control logic
  3. Group A and Group B control
  4. Port A and Port B
  5. Port C
8255 block diagram

1. Data Bus Buffer

  • The 8 bit bidirectional tristate data bus buffer is used to interface 8255 internal data bus with system data bus.
  • The direction of data buffer is decided by read and write control signals.
  • When read is activated, it transmits data to the system data bus.
  • When write is activated, it receives data from system data bus.

2. Read/Write Control Logic

  • This block accepts inputs from system control bus and address bus and performs operations.
  • The control signals are \overline{RD} and \overline{WR} and address signals used are A0 and A1 and \overline{CS}.
  • The signls \overline{RD} and \overline{WR} are connected to \overline{IOR}, \overline{IOW} or \overline{MEMR}, \overline{MEMW}.
  • A0 and A1 of 8085 are directly connected to address lines A0 and A1 of 8255.
  • \overline{CS} is connected to address chip select decoder.
  • The 8255 operation/selection is enabled/disabled by \overline{CS} signal.

3. Group A and Group B Control

  • The 8255 I/O ports are divided into 2 sections. Group A(GA) and Group B(GB).
  • Group A consist of port A and port C upper.
  • Group B consist of port B and port C lower.
  • Each group is programmed through software.
  • The GA and GB control block receives commands from R/W control logic to accept bit pattern from CPU.
  • GA control will control GA ports and GB control will control GB ports.
  • The bit pattern given by CPU consist of information:
    • To control the operation of GA and GB
    • The mode in which they should be operated.

4. Port A and Port B

  • Port A and port B consist of an 8-bit bidirectional data output latch/buffer and an 8-bit data input buffer.
  • The function of ports A and B is decided by the control bit pattern available in GA and GB control.
  • The function of ports A and B are also independent of the mode of operation.

5. Port C

  • The port C consists of an 8-bit bidirectional data output latch/buffer and an 8-bit data input buffer.
  • It is divided into 2 sections, port C upper PCU and port C lower PCL. These two sections can be programmed and used separately as a 4-bit I/O port.
  • It can be used as (i)Simple I/O (ii) handshake signals (iii) status signal inputs.
  • For handshake signals and status signals, it is used in coordination with port A and port B.
  • The direct but set/reset capability is provided by port C only.

8255 PPI Operating Modes

  • The 8255 IC provides one control word register.
  • It is selected when A0=1, A1=1, \overline{CS} =0 and \overline{WR} = 0.
  • The read operation is not allowed for control register.
  • The bit pattern loaded in control word register specify an I/O function for each port and the mode of operation in which the ports are to be used.
  • There are 2 different control word formats which specify 2 basic modes:
    1. BSR-Bit set reset mode
    2. I/O mode
  • The two basic modes are selected by D7 bit of control register. When D7=1, it is a I/O mode and when D7 =0, it is a BSR mode.

1. BSR Mode

  • The BSR mode is a port C bit set/reset mode.
  • The individual bit of port C can be set or reset by writing control word in the control register.
  • The control word format of BSR mode is as shown in the figure below:
8055 PPI BSR Mode
  • The pin of port C is selected using bit select bits [b b b] and set or reset is decided by bit S/R.
  • The BSR mode affects only one bit of port C at a time.
  • The bit set using BSR mode remains set unless and until you change the bit. So to set any bit of port C, bit pattern is loaded in control register.
  • If a BSR mode is selected, it will not affect I/O mode.

2. I/O Modes

There are three I/O modes of operation:

  1. Mode 0 : Basic I/O
  2. Mode 1 : Strobed I/O
  3. Mode 2 : Bidirectional I/O

I/O modes are programmed using a control register.

8055 PPI I/O Mode

The function of each bit is as follows:

  1. D7: When the bit D7=1 then I/O mode is selected, if D7=0 then BSR mode is selected. The function of bits D0 to D6 is dependent on mode.
  2. D6 and D5: In I/O mode the bit D6 and D5 specifies the different I/O modes for group A.
  3. D4 and D3: In I/O mode the bits D4 and D3 selects the port function for groups A. If these bits =1 the respective port specified is used as input port. But if bit=0, the port is used as output port.
  4. D2: In I/O mode the bit D2 specifies the different I/O modes for group B.
  5. D1 and D0: In I/O mode the bits D1 and D0 selects the port function for group B. If these bits =1 the respetive port specified is used as input port. But if bit=0, the port is used as output port.

8255 PPI Applications

8255 PPI is the most widely used chip for many applications like:

  • LED / Relay Interface
  • Display Interface
  • Stepper Motor Interface
  • Lift Controller etc.
  • Key board Interface
  • ADC / DAC Interface
  • Traffic Signal Controller
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