8255 PPI (Programmable Peripheral Interface)

In this lecture, we are going to learn about the most important device of the 8085 microprocessor which is the 8255 PPI (Programmable Peripheral Interface) in very detail. So let’s start with the introduction of 8255 PPI.

Table of Contents

Introduction

The 8255 PPI is a programmable peripheral interface device.
It is a general-purpose programmable parallel I/O device.
It contains 3 I/O ports which can be programmed in different modes.
To program the function to all three i/O ports t contains a register called control registers. The control register defines the function of each I/O port and in which mode they should operate.
8055 PPI is general purpose in nature and provides many facilities for connecting different devices. So it is used frequently in different applications.

Features of 8255 PPI

It is a programmable parallel I/O device.
It contains 24 programmable I/O pins arranged as 2-8 bit ports and 2-4 bit ports.
It has 3, 8-bit ports: Port A, Port B, and Port C, which are arranged in two groupss of 12 pins.
Fully compatible with Intel microprocessor families.
TTL is compatible.
Direct bit set/reset capability is available for port C.
Improved DC driving capability.
It can operate in 3 Modes:
1. Mode 0: Simple I/O
2. Mode 1: Strobed I/O
3. Mode 2: Strobed bi-directional I/O

Pin Configuration of 8255 PPI

The pin configuration of 8255 PPI (Programmable Peripheral Interface) is as shown in the figure below:

PA₀-PA₇	I/O	Port A pins
PB₀-PB₇	I/O	Port B pins
PC₀-PC₇	I/O	Post C pins
D₀-D₇	I/O	Data pins
RESET	I	Reset input
$\overline{RD}$	I	Read input
$\overline{WR}$	I	Write input
A₀-A₁	I	Address pins
$\overline{CS}$	I	Chip select
VCC-GND	I	+5 V supply ground

Symbol	Name	Function
D₀-D₇	Data Bus	These are 8-bit bi-directional data bus lines, connected to the system data bus for data transfer between CPU and 8255.
$\overline{CS}$	Chip select	These are input, active HIGH address lines used to distinguish different ports of 8255 such as Port A, Port B, Port C, and Control register.
$\overline{RD}$	Read	This is an active low input signal used in coordination with another signal to send data to the CPU through data lines.
$\overline{WR}$	Wite	This is an active low input signal used in coordination with another signal to send data to 8255.
A₀-A₁	Address lines	These are input, active HIGH address lines used to distinguish different ports of 8255 such as Port A, Port B, Port C, Control register.
RESET	Reset	This is an active HIGH input signal used to reset 8255. When 8255 is reset, it clears the control word register and all ports are set to input mode.
PA₀-PA₇	Port A pins 0 to 7	These are 8-bit bidirectional I/O pins used to send data to the peripheral or to read data from the peripheral. The contents are transferred to/from Port A.
PB₀-PB₇	Port B pins 0 to 7	These are 8-bit bidirectional I/O pins used the same as PA₀-PA₇
PC₀-PC₇	Port C pins 0 to 7	These are 8-bit bidirectional I/O pins. These lines are divided into 2 sections i.e. PC₀-PC₃ and PC₄-PC₇. These two sections can be individually used to transfer 4 bits of data from two separate port C sections.

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8255 PPI Functional Block Diagram

The block diagram of 8255 PPI is shown in the figure below:

It contains the following blocks

Data bus buffer
Read/Write control logic
Group A and Group B control
Port A and Port B
Port C

1. Data Bus Buffer

The 8-bit bidirectional tristate data bus buffer is used to interface the 8255 internal data bus with the system data bus.
The direction of the data buffer is decided by read and write control signals.
When the read is activated, it transmits data to the system data bus.
When a write is activated, it receives data from the system data bus.

2. Read/Write Control Logic

This block accepts inputs from the system control bus and addresses bus and performs operations.
The control signals are $\overline{RD}$ and $\overline{WR}$ and address signals used are A₀ and A₁ and $\overline{CS}$ .
The signls $\overline{RD}$ and $\overline{WR}$ are connected to $\overline{IOR}$ , $\overline{IOW}$ or $\overline{MEMR}$ , $\overline{MEMW}$ .
A₀ and A₁ of 8085 are directly connected to address lines A₀ and A₁ of 8255.
$\overline{CS}$ is connected to address chip select decoder.
The 8255 operation/selection is enabled/disabled by $\overline{CS}$ signal.

3. Group A and Group B Control

The 8255 I/O ports are divided into 2 sections. Group A(GA) and Group B(GB).
Group A consist of port A and port C upper.
Group B consists of port B and port C lower.
Each group is programmed through software.
The GA and GB control block receives commands from R/W control logic to accept bit pattern from the CPU.
GA control will control GA ports and GB control will control GB ports.
The bit pattern given by the CPU consists of the following information:
- To control the operation of GA and GB
- The mode in which they should be operated.

4. Port A and Port B

Port A and port B consist of an 8-bit bidirectional data output latch/buffer and an 8-bit data input buffer.
The function of ports A and B is decided by the control bit pattern available in GA and GB control.
The function of ports A and B are also independent of the mode of operation.

5. Port C

Port C consists of an 8-bit bidirectional data output latch/buffer and an 8-bit data input buffer.
It is divided into 2 sections, port C upper PC_U and port C lower PC_L. These two sections can be programmed and used separately as a 4-bit I/O port.
It can be used as (i)Simple I/O (ii) handshake signals (iii) status signal inputs.
For handshake signals and status signals, it is used in coordination with port A and port B.
The direct but set/reset capability is provided by port C only.

8255 PPI Operating Modes

The 8255 IC provides one control word register.
It is selected when A0=1, A1=1, $\overline{CS}$ =0 and $\overline{WR}$ = 0.
The read operation is not allowed for the control register.
The bit pattern loaded in the control word register specifies an I/O function for each port and the mode of operation in which the ports are to be used.
There are 2 different control word formats that specify 2 basic modes:
1. BSR-Bit set-reset mode
2. I/O mode
The two basic modes are selected by the D7 bit of the control register. When D7=1, it is an I/O mode, and when D₇ =0, it is a BSR mode.

1. BSR Mode

The BSR mode is a port C bit set/reset mode.
The individual bit of port C can be set or reset by writing the control word in the control register.
The control word format of BSR mode is as shown in the figure below:

The pin of port C is selected using bit select bits [b b b] and set or reset is decided by bit S/R.
The BSR mode affects only one bit of port C at a time.
The bit set using BSR mode remains set unless and until you change the bit. So to set any bit of port C, the bit pattern is loaded in the control register.
If a BSR mode is selected, it will not affect the I/O mode.

2. I/O Modes

There are three I/O modes of operation:

Mode 0: Basic I/O
Mode 1: Strobed I/O
Mode 2: Bidirectional I/O

I/O modes are programmed using a control register.

The function of each bit is as follows:

D₇: When the bit D7=1 then I/O mode is selected, if D7=0 then BSR mode is selected. The function of bits D0 to D6 is dependent on mode.
D₆ and D₅: In I/O mode the bit D6 and D5 specify the different I/O modes for group A.
D₄ and D₃: In I/O mode the bits D4 and D3 select the port function for groups A. If these bits =1 the respective port specified is used as the input port. But if bit=0, the port is used as the output port.
D₂: In I/O mode the bit D2 specifies the different I/O modes for group B.
D₁ and D₀: In I/O mode the bits D1 and D0 select the port function for group B. If these bits =1 the respective port specified is used as the input port. But if bit=0, the port is used as the output port.

8255 PPI Applications

8255 PPI is the most widely used chip for many applications:

LED / Relay Interface
Display Interface
Stepper Motor Interface
Lift Controller etc.

Keyboard Interface
ADC / DAC Interface
Traffic Signal Controller

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