Instruction Set of 8085 Microprocessor | Classification of Instruction set of 8085 Microprocessor

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In this lecture, we are going to learn about what is instructions, Instruction set of 8085 microprocessor, and the classification of instruction set of 8085 microprocessors. so let’s discuss it one by one in a detailed manner.

Introduction of Instruction

An instruction is a binary pattern designed inside a microprocessor to perform a specified function. In another word, we can say An instruction is a command given task on specified data.

Each instruction has two parts:

  1. One is the task to be performed, called the “operation code” (OPCODE).
  2. Second is the data to be operated on called the “OPERAND”.

The operand  ( or data) may include 8-bit or 16-bit data, on the internal register, a memory location, or an 8-bit or 16-bit address.

Introduction of Instruction Sets

The instruction set is a collection of Instructions of  Microprocessor, that determines what functions that microprocessor can perform.

In data transfer, the contents of the source are not destroyed; only the contents of the destination are changed.

An I/O device can transfer or receive data from the accumulator but not from other registers (except for the memory-mapped I/O device).

Arithmetic and logical operations are performed with the contents of the accumulator, and the results are stored in the accumulator.

Any register including memory can be used for increment and decrement.

A program sequence can be changed either conditionally or by testing for given data conditions.

In some instructions, data is implied. Most instructions of this type operate on the content of the accumulator.

Classification of Instruction Set of 8085

classification of instruction set of 8085

Types of Instruction set of  8085 based on Length of Word size

1-byte or One-word Instruction set of 8085

  • A one-byte instruction includes the opcode and the operand in the same byte.
  • Examples of this type are:
    • MOV A, B
    • ADD B
    • RAL
    • CMA, etc.

For 1-byte Instruction:

Task Opcode Operand
Copy the contents of the accumulator in Register C MOV C, A
Add the contents of the register B to the contents of the  accumulator ADD B
Invert  (Complement) each bit in the accumulator CMA  
  • The above instructions are 1-byte instructions performing three different tasks.
  • In the first instruction, both operand registers are specified.
  • In the second instruction, operand B is specified and the accumulator is assumed.
  • Similarly, in the third instruction, the accumulator is assumed to be the implicit operand.
  • These instructions are stored in an 8-bit binary format in memory; each requires one memory location.

2-byte or 2-word Instruction set of 8085

  • In a 2-byte instruction, the 1st-byte specifies the opcode and the 2nd-byte specifies the operand.
    • MVI B, 05
    • IN 01 etc.

For 2-byte Instruction:

Task Opcode Operand Hex Code
Load an 8-bit data byte in the accumulator MVI A, Data 1st byte, data 2nd byte
  • Assume the data byte is 32H. The assembly language instruction is written as:
    • Mnemonics: MVI A, 32H
  • This instruction would require two memory locations to store n memory.

3-byte or 3-word Instruction set of 8085

  • In a 3-byte instruction, the 1st byte specifies the opcode, and the following two bytes specify the 16-bit address such that the 2nd byte is a low order address and the 3rd-byte is high order address.
    • LXI H, 2400H
    • LDA 2500H
    • JMP 2085H etc.

For 3-byte Instruction:

Task Opcode Operand Hex Code
Transfer the program sequence to the memory location 2085H JMP 2085 H C3 is 1st byte, 85 2nd byte, and 20 3rd byte.
  •  This instruction would require three memory locations to store in the memory.

Types of Instruction set of  8085 based on Addressing Modes:

1.Direct Addressing Mode Instruction set of 8085

  • In this instruction set, the direct address contains the address of operand within the instruction itself.
    • LDA 2600 H
    • IN 05
    • OUT 07
    • STA 2700 H

2.Register Addressing Mode Instruction set of 8085

  • In this type of instruction set, operands will be present in the micro-process registers.
    • MOV A, B
    • ADD B
    • SUB C

3.Register Indirect Addressing Mode Instruction set of 8085

  • In this type of instruction, the operands will present in memory (M) and the address of memory is present register pair.
  • It is also called “indirect addressing mode type instruction set”.
    • MOV A, M
    • ADD M
    • LDAX B

4.Immediate Addressing Mode Instruction set of 8085

  • In this type, the operand and data are specified within the instruction itself.
  • In other words, we can say, this type of instruction has an operand field rather than an address field.
    • MVI A, 25
    • ADI 36

5.Implicit Addressing Mode Instruction set of 8085

  • If operations of the microprocessor are performed by accumulator alone or machine control instructions, then it contains an implied addressing type.
    • e.g. CMA, RAL, DAA

Also Read:

Types of Instruction set of  8085 based on Operation Modes

1.Data Transfer Instruction set of 8085

Read in deep: Data Transfer Instructions in 8085 in detailed manner

In this group, the data in transfer,

  • From register to register
  • Between memory and register
  • Between I/O and accumulator
  • Load an 8-bit number in a register
  • Load 16-bit number in a register pair.
Instruction Set Meaning Example Addressing Mode T-States Machine Cycle Affected Flags Bytes of Instruction

MOV r1, r2

[r1] ← [r2]

Move content of one register to another register  MOV A, B

Register addressing mode

4T 1 MC None 1-byte

MOV r, M

[r] ← [M] or

[r] ← [[H,L]]

Move content of memory to register

MOV B, M

Register indirect addressing mode

7T 2 MC None 1-byte

MOV M, r

[M] ← [r] or

[[H,L]]  ← [r]

Move content of register to memory

MOV M, C

Register indirect addressing mode

7T 2 MC None 1-byte

MOV r, data

[r] ← data

Move immediate data to register

MOV A, 05H

Immediate addressing mode

7T 2 MC None 2-byte

LXI rp, 16-bit data

[rp] ← 16-bit data;

[rh] ← 8 MSBs of data,[rl] ← 8 LSBs of data

Load register pair immediately

LXI H, 2800H, i.e. [L] ← [00],[H] ← [28]

Immediate addressing mode

10T 3 MC None 3-byte

LDA address

[A] ← [[address]]

Load accumulator direct

LDA  2400H

direct addressing mode

13T 4 MC None 3-byte

STA address

[[address]] ← [A]

store accumulator direct

STA  2000H

direct addressing mode

13T 4 MC None 3-byte

LHLD address

[L] ← [[address]],

[H] ← [[address + 1]]

Load H-L pair direct

LHLD  2500H

direct addressing mode

16T 5 MC None 3-byte

SHLD address

[[address]] ← [L],[[address + 1]] ← [H]

store H-L pair direct

SHLD  2500H

direct addressing mode

16T 5 MC  None 3-byte

LDAX rp

[A] ← [[rp]]

Load accumulator indirect

LDAX B

Register indirect addressing mode

7T 2 MC None 1-byte

STAX rp

[[rp]] ← [A]

store accumulator indirect

STAX D

Register indirect addressing mode

7T 2 MC None 1-byte

XCHG

[H-L] ↔ [D-E]

Exchange the content of H-L pair with D-E pair

XCHG

Register addressing mode

4T 1 MC None 1-byte

MVI M, data

[[H-L]] ← [data] or [M] ← [data]

Move immediate data to memory

LXI H , 2400H  

MVI M, 08         

HLT            

 

Register indirect addressing mode

10T 3 MC None 2-byte

2.Arithmetic Group Instruction set of 8085

In this group, the data is performed as addition, subtraction, increment (add 1), decrement (subtract 1), etc.

The arithmetic operations implicitly assume that the content of the accumulator is one of the operands.

The results of the arithmetic operations are stored in the accumulator, thus the previous content of the accumulator is altered.

The flags are modified to reflect the data conditions of an operation.

The content of a register is not changed as a result of an arithmetic operation.

In the add operation, if the sum is larger than 8-bit, CY is set.

The subtraction operation is performed by using 2’s complement method and CY is complemented after subtraction.

If a subtraction results in a negative number, the answer is in 2’s complement and CY is set.

In unsigned arithmetic operations, the sign flag(S) should be ignored.

The instructions INR (Increment) and DCR (Decrement) are special cases of arithmetic operations.

Instruction Set Meaning Example Addressing Mode T-States Machine Cycle Affected Flags Bytes of Instruction

ADD r

[A]← [A] + [r]

Add register to the accumulator ADD B Register addressing mode 4T 1 MC All  1-byte

ADC r

[A]← [A] + [r] + [C]

Add register with carry to the accumulator ADC D Register addressing mode 4T 1 MC All  1-byte

ADD M

[A]← [A] + [M] or

[A]← [A] + [[H-L]]

Add memory to accumulator ADD M Register indirect addressing mode 7T 2 MC All 1-byte

ADC M

[A]← [A] + [M] + [C] or

[A]← [A] + [[H-L]] + [C]

Add memory with carry to accumulator ADC M Register indirect addressing mode 7T 2 MC All 1-byte

ADI data

[A]← [A] + data

Add immediate data to the accumulator ADI 08H Immediate addressing mode 7T 2 MC All 2-byte

ADI data

[A]← [A] + data + [C]

Add immediate data with carry to the accumulator ACI 08H Immediate addressing mode 7T 2 MC All 2-byte

SUB r

[A]← [A] – [r]

Subtract register from the accumulator SUB B Register addressing mode 4T 1 MC All 1-byte

SBB r

[A]← [A] – [r] – [C]

Subtract register from the accumulator with borrow SBB B Register addressing mode 4T 1 MC All 1-byte

SUB M

[A]← [A] – [M] or

[A]← [A] – [[H-L]]

Subtract memory from the accumulator SUB M Register indirect addressing mode 7T 2 MC All 1-byte

SBB M

[A]← [A] – [M] – [C] or

[A]← [A] – [[H-L]] – [C]

Subtract memory from the accumulator with borrow SBB M Register indirect addressing mode 7T 2 MC All 1-byte

SUI data

[A]← [A] – data

Subtract immediate data from the accumulator SUI 01H Immediate addressing mode 7T 2 MC All 2-byte

SBI data

[A]← [A] – data – [C]

Subtract immediate data from the accumulator with borrow SBI 01H Immediate addressing mode 7T 2 MC All 2-byte

INR r

[r]← [r] + [01]

Increment register content by 1 INR D Register addressing mode 4T 1 MC All except CY 1-byte

INR M

[M]← [M] + [01] or

[[H-L]]← [[H-L]] + [01]

Increment the memory content by 1 INR M Indirect Register addressing mode 10T 3 MC All except CY 1-byte

INX rp

[rp]← [rp] + [0001]

Increment the content of register pair by 1 INX D Register addressing mode 6T 1 MC None 1-byte

DCR r

[r]← [r] – [01]

Decrement register content by 1 DCR D Register addressing mode 4T 1 MC All except CY 1-byte

DCR M

[M]← [M] – [01] or

[[H-L]]← [[H-L]] – [01]

Decrement the memory content by 1 DCR M Indirect Register addressing mode 10T 3 MC All except CY 1-byte

DCX rp

[rp]← [rp] – [0001]

Decrement the content of register pair by 1 DCX D Register addressing mode 6T 1 MC None 1-byte

DAA

Decimal adjust accumulator after addition DAA Implicit addressing mode 4T 1 MC All 1-byte

DAD rp

[[H-L]]← [[H-L]] + [rp]

Double addition register pair DAD H Register addressing mode 10T 3 MC only CY  1-byte

3.Logical Group Instruction set of 8085

The instruction set of this group performs AND, OR, EXOR operations, compare, rotate or take the complement of data in register or memory.

The process of performing logic operations through the software instructions is slightly different from the hardwired logic.

Logic operations are performed n relation to the content of the accumulator.

Logic operations simulate eight 2-input gates ( or inverters).

The sign, zero (and parity) flags are modified to reflect the status of operations. The carry flag is reset. However, the NOT operation does not affect any flags.

After a logic operation has been performed, the answers are placed in the accumulator replacing the original content of the accumulator.

The logic operations cannot be performed directly with the content of two registers.

The individual bits in the accumulator can be set or reset using logic instructions.

Instruction Set Meaning Example Addressing Mode T-States Machine Cycle Affected Flags Bytes of Instruction

ANA r

[A] ← [A] ∧ [r]

AND register with the accumulator ANA B Register addressing mode 4T 1 MC All and AC=1, CY=0 1-byte

ANA M

[A] ← [A] ∧ [M] or

[A] ← [A] ∧ [[H-L]]

AND memory with the accumulator ANA M Register indirect addressing mode 7T 2 MC All and AC=1, CY=0 1-byte

ANI data

[A] ← [A] ∧ data

AND immediate data with the accumulator ANI 01H Immediate addressing mode 7T 2 MC All and AC=1, CY=0 2-byte

ORA r

[A] ← [A] ∨ [r]

OR register with the accumulator ORA B Register addressing mode 4T 1 MC All and AC=0, CY=0 1-byte

ORA M

[A] ← [A] ∨ [M] or

[A] ← [A] ∨ [[H-L]]

OR memory with the accumulator ORA M Register indirect addressing mode 7T 2 MC All and AC=0, CY=0 1-byte

ORI data

[A] ← [A] ∨ data

OR immediate data with the accumulator ORI 01H Immediate addressing mode 7T 2 MC All and AC=0, CY=0 2-byte

XRA r

[A] ← [A] ” data

EXOR register with the accumulator XRA B Register addressing mode 4T 1 MC All and AC=0, CY=0 1-byte

XRA M

[A] ← [A] ” [M] or

[A] ← [A] ” [[H-L]]

EXOR memory with the accumulator XRA M Register indirect addressing mode 7T 2 MC All and AC=0, CY=0 1-byte

XRI data

[A] ← [A] ∨ data

EXOR immediate data with the accumulator XRI 01H Immediate addressing mode 7T 2 MC All and AC=0, CY=0 2-byte

CMA

[A] → [Ā]

Complement the accumulator CMA Implicit addressing mode 4T 1 MC None 1-byte

CMP r

Compare register with accumulator CMP B Register addressing moder 4T 1 MC All 1-byte

CMP M

[A] ← [A] – [M]

Compare memory with accumulator CMP M Register indirect addressing mode 7T 2 MC All 1-byte

CPI data

[A] ← [A] – [data]

Compare immediate data with accumulator CMP 01H Immediate addressing mode 7T 2 MC All 2-byte

CMC

[CS] ← [CS’]

Complement the carry status CMC   4T 1 MC No flag except CY flag 1-byte

STC

[CS] ← 1

Set carry status STC   4T 1 MC  No flag except CY 1-byte

RLC

[An+1] ← [An]

[Ao] ← [A7]

[CY] ← [A7]

Rotate accumulator left. The content of the accumulator is rotated left by one bit.   Implicit addressing mode 4T 1 MC only CY 1-byte

RRC

[An] ← [An+1]

[A7] ← [A0]

[CY] ← [A0]

Rotate accumulator right. The content of the accumulator is rotated right by one bit.  RRC Implicit addressing mode 4T 1 MC  only CY 1-byte

RAL

[An+1] ← [An]

[CS] ← [A7]

[A0] ← [CS]

Rotate accumulator left through carry. The content of the accumulator is rotated left one bit through carry.

RAL Implicit addressing mode 4T 1 MC  only CY 1-byte

RAR

[An] ← [An+1]

[CS] ← [A0]

[A7] ← [CS]

Rotate accumulator right through carry. The content of the accumulator is rotated right one bit through carry.

RAR Implicit addressing mode 4T 1 MC  only CY 1-byte

4.Branch Group Instruction set of 8085

The Branch Instructions are the most powerful instructions because they allow the microprocessor to change the sequence of a program, either unconditionally or under certain test conditions.

These instructions are the key to the flexibility and versatility of a computer.

These are classified into 3 categories:

  1. JUMP instructions 
  2. CALL and RETURN instructions 
  3. RESTART instructions.

JMP Instruction:

Unconditional JMP Instructions:

  • This instruction enables the programmer to set up a continuous loop.
  • When this instruction is executed then PC content will become a specified address and the next instruction execution will start from the given address memory location.
  • 3-byte instruction
  • Immediate addressing mode
  • 3 MC 
  • 10 T-states

Conditional JMP Instructions:

  • This instruction allows the microprocessor to make decisions based on certain conditions indicated by the flags.
  • The conditional jump instruction checks the flag conditions and makes decisions to change or not to change the sequence of a program.
  • Out of five flags, 4 (CY, Z, S, and P) flags are used by conditional JMP, but the AC flag is not used.
Opcode Operand Description
JC 16-bit Jump on carry ( if result generates carry and CY=1 )
JNC 16-bit Jump on no carry ( CY=0 )
JZ 16-bit Jump on zero ( if result is zero and Z=1 )
JNZ 16-bit Jump on no zero ( Z=0 )
JP 16-bit Jump on plus ( if D7=0 and S=0 )
JM 16-bit Jump on minus ( if D7=1 and S=1 )
JPE 16-bit Jump on even parity ( P=1 )
JPO 16-bit Jump on add parity ( P=0 )

CALL Instruction:

  • It is used in the main program to call a subroutine.
  • When a subroutine is called, the contents of PC, which is the address of the instruction following the CALL instruction, is stored on the stack and the program execution is transferred to the subroutine address.

Unconditional CALL Instructions:

  • When it is executed, the microprocessor will store the address of the next instruction in STACK and the PC is located with a subroutine address.
  • 3-byte instruction
  • Immediate/Register indirect mode
  • 5 MC
  • 18 T-States
  • No flags are affected

Conditional CALL Instructions:

  • In this case, the program is transferred to the subroutine if the condition is met and this time it requires 5 MC and 18 T-States.
  • If the condition is not met then the main program is continued and it requires 2 MC and 9 T-states.
  • In this instruction, all flags are used except the AC flag. 
Opcode Operand Description
CC 16-bit Call subroutine if carry flag is set ( CY = 1)
CNC 16-bit Call subroutine if carry flag is reset (CY = 0)
CZ 16-bit Call subroutine if zero flag is set ( Z=1 )
CNZ 16-bit Call subroutine if zero flag is reset ( Z=0 )
CM 16-bit Call subroutine if sign flag is set ( S=1, negative number)
CP 16-bit Call subroutine if sign flag is reset ( S=0, positive number)
CPE 16-bit Call subroutine if parity flag is set ( P=1, even parity)
CPO 16-bit Call subroutine if parity flag is reset ( P=0, odd parity)

RETURN Instruction:

  • It is used at the end of the subroutine to return to the main program.
  • When RET instruction is executed as the end of the subroutine, the memory address stored on the stack is retrieved, and the sequence of execution is resumed in the main program.

Unconditional RET Instructions:

  • It will change the program sequence from subroutine to the main program.
  • 1-byte instruction
  • Implicit addressing mode
  • 3 MC
  • 10 T-states
  • No flags are affected.

Conditional RET Instructions:

  • In this case, the sequence of the program returns to the main program if the condition is met and at this time it requires 3 MC and 12 T-States.
  • If the condition is not met then the sequence of the program is continued in the subroutine and it requires 1-MC and 6 T-states.
  • In this instruction, all flags are used except the AC flag.
Opcode Operand Description
RC 16-bit Return if carry flag is set (CY=1)
RNC 16-bit Return if carry flag is reset (CY=0)
RZ 16-bit Return if zero flag is set (Z=1)
RNZ 16-bit Return if zero flag is reset (Z=0)
RM 16-bit Return if sign flag is set (S=1, negative number)
RP 16-bit Return if sign flag is reset (S=0, positive number)
RPE 16-bit Return if parity flag is set (P=1, even parity)
RPO 16-bit Return if parity flag is reset (P=0, odd parity)

5.Stack, I/O and Machine Control Group Instruction set of 8085

The stack in an 8085 microprocessor is a group of memory locations in the R/W memory that is used for the temporary storage of binary information during the execution of the program.

PUSH, POP, SPHL, XHTL are the example of instruction of stack group.

IN, OUT are the example of I/O group.

NOP, EI, D, SIM, RIM, HLT are examples of the machine control groups.

Instruction Set Meaning Example Addressing Mode T-States Machine Cycle Affected Flags Bytes of Instruction

PUSH rp

[[SP-1]] ← [rh]

[[SP-2]] ← [rl]

[SP] ← [SP] – 2

Push the content of register pair to stack PUSH H Register indirect addressing mode 12T 3 MC None 1-byte

POP rp

[rl] ← [[SP]]

[rh] ← [[SP] + 1]

[SP] ← [SP] + 2

Pop the content of register pair to stack which was saved from the stack POP H Register indirect addressing mode 10T 3 MC None 1-byte

SPHL

[H-L] → [SP]

Move the content of H-L pair to SP SPHL Register addressing mode 6T 1 MC

None

1-byte

XTHL

[L] → [[SP]]

[H] → [[SP] + 1 ]

Exchange stack top with H-L pair XTHL Register indirect addressing mode 16T 5 MC

None

1-byte

IN Port address

[A] ← [Port]

Input to accumulator from I/O Port

IN 05

[Accumulator] ← [[05]]

Direct addressing mode 10T 3 MC

None

2-byte

OUT Port address

[Port] ← [A]

Output from the accumulator to I/O Port

OUT 05

[[05]] ← [Accumulator]

Direct addressing mode 10T 3 MC

None

2-byte

HLT

Halt

HLT

Implicit addressing mode 5T 1 MC

None

1-byte

NOP

RIM

SIM

DI

EI

No operation

Read interrupt mask

Set interrupt mask

DIsable interrupt

Enable Interrupt

  All implicit addressing mode all 4T  all 1 MC

None

All 1-byte

Do You Know?

  1. Which Logic can be used to set the bit?

    OR-Logic

  2. Which Logic can be used to reset the bit?

    AND -Logic

  3. Which instruction can be made the content of the accumulator zero?

    XRA A

  4. Which instruction is used to clear the lower 4-bits of the accumulator in the 8085 microprocessor?

    ANI F0H

  5. Which programming is used in the design of the control unit?

    Microprogramming

  6. In which principle does STACK works?

    LIFO (Last in First Out)

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Electronics Engineering(2014 pass out) Junior Telecom Officer(B.S.N.L.) Project Development, PCB designing Teaching of Electronics Subjects

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