This section will show the Generation of time delay in 8085 programs. The delay will be used in different places to simulate clocks, counters, or other areas.
Before starting the topic, we will get the information about what delay is.
The dictionary meaning of delay is Operating after some time. Thus delay is related to the time parameter.
Generation of time delay in 8085
The question is, where do we require it?
- The simple example 1 can give you is of a timer. Suppose I want a timer circuit which will switch ON air condition in the office at 9.00 a.m. and switch it OFF at 6.00 p.m. It means the circuit has to make the A.C. ON and provide a delay of 9 hours, to make it off again.
- In the same way in traffic signals, switch on the RED, yellow, and green lights one by one, after certain a Time delay. Thus, delay is most widely used in digital clocks, process control, serial communication, etc.
Now the important point is, how to provide time delay in microprocessors?
- In microprocessors, we have studied different instructions, like NOP, DCR, and DCX. One can use those instructions, execute it a number of times, and get a “delay“.
- The delay we achieved is due to software instructions. Therefore, it is referred to as a “software delay.”
Note: Here the important hint is, that we know that, to execute a particular instruction, the microprocessor takes a fixed amount of time. The microprocessor is driven by fixed and constant frequency i.e. quartz crystal. Therefore using instruction, it is possible to provide delay. But for that, you need to know a number of T states required to execute particular instruction and the clock frequency.
Delay Using NOP Instruction
- During the execution of an NOP instruction the microprocessor does not perform any internal operations, hence it is used to provide a delay between two events or instructions. It requires one machine cycle (OPCODE fetch cycle). The length of this machine cycle is 4T states.
- Therefore, the delay provided by one NOP instruction is,
- Suppose the T state or clock cycle has a frequency of 2 MHz, then the time duration of the clock will be = 1/2MHz
- Therefore, using NOP instruction we get,
- If we want more delay than 4T, then we go on increasing NOP after NOP, but it becomes impractical as the size of the program increases.
Timing Delay Using Counters
Counting can also create timing delays. The execution time of a program or the instructions are known to the user. By means of this data, a user can determine the amount of time delay.
Timing delay using an 8-bit counter
- Consider the delay subroutine given below,
| Label | Instruction | Comments | Number of T-States |
|---|---|---|---|
| MVI C, Count | Load count | 7 T-states | |
| L1: | DCR C | Decrement count | 4 T-states |
| JNZ L1 | If count ≠ 0, continue | 10/7 T-states |
- The time required for the execution of this program can be calculated with the T-states. If the JNZ condition is met (Z = 0) then 10 T states are required and then the program branches to the DCR C instruction. If the JNZ condition is not met (Z = 1) then 7 T-states are required and the program executes the next instruction after the JNZ instruction. For every iteration in which the JNZ condition is met (Z = 0), the number of cycles is equal to cycles for DCR C + cycles for JNZ = 4+10= 14 cycles.
- These 14 cycles will be performed at times. In the last iteration, the (count – 1 ) condition is met. Hence, no jump operation. So the number of T-states cycles is cycles for DCR C + cycles for JNZ = 4 + 7 = 11 cycles.
- ∴ The total T-states required to execute a given program are, = 7+ (count-1)x(10+4)+(4+7) MVI C Iterations/Loops Last Iteration
- For count = 2
- Number of T-states = 7 + (2 – 1) * 14 + 11 = 7 + 14 + 11 = 32
- Assuming the operating frequency of 8085 A is 5 MHz
- Time required for 1 T-state = 1/(5MHz) =0.2 µsec
∴ Time required for executing the above program = 32 * 0.2 µsec=6.4 µsec
The maximum count that can be loaded in an 8-bit register is FFH (i.e. 25510). Hence, the maximum delay possible with the 8-bit count, assuming operating frequency 5 MHz = 714.8 µsec.
From these calculation we can see that a delay with the 8-bit count is feasible for a small delay. For a larger delay, we need to use a 16-bit counter.
Timing delay using a 16-bit counter
- Consider the subroutine given below:
| Label | Instructions | Comments | T-States |
|---|---|---|---|
| LXI D, Count | Load 16-bit count | 10 T-states | |
| L1: | DCX D | Decrement count | 6 T-states |
| MOV A, D | 4 T-states | ||
| ORA E | logically OR D and E | 4 T-states | |
| JNZ L1 | If the result ≠ 0, continue | 10/7 T-states |
- The instruction LXI D, count is executed only once. The number of T-states required for an iteration equals T-states of DCX D + T-states of MOV A, D + T-states of ORA E+T-states of JNZ = 6+4+4+10 = 24 T states.
- The T-states the last iteration requires are T-states of DCX D + T-states of MOV A, D+T-states of ORA E + T-states of JNZ = 6+4+4+7=21 T-states.
∴ Total T states required by program are = 10 + (count-1) × 24 + 21
For count = 0FFFH (4095)10
Number of T states = 10+4094 × 24+21= 98287
- Assuming operating frequency = 5 MHz
- Time required for 1 T-states = 1/5 MHz = 0.2 µsec
∴ Time required for execution of above program = 98287 × 0.2 µsec = 19657.4 µsec = 19.657 µsec
- Maximum delay that can be achieved using 16-bit count FFFF H (65535)10 and 5 MHz operating frequency is = (10+ (65535-1) × 24+ (21)) x 0.2 µsec = 0.314569 sec
In case if our application requires delays more than this, then nested loops can be used for implementing timing delays.
Timing Delay Using nested Loops
- Consider the following subroutine:
| Label | Instruction | Comments | T-states |
|---|---|---|---|
| MVI D, multiplier count | Initialize multiplier | 7 T-states | |
| L2: | MVI C, delay count | Initialize delay count | 7 T-states |
| L1: | DCR C | decrement count | 4 T-states |
| JNZ L1 | if the delay count ≠ 0, continue | 10/7 T-states | |
| DCR D | decrement multiplier count | 4 T-states | |
| JNZ L2 | if the multiplier count ≠ 0, continue | 10/7 T-states |
- In this method, there are more than some loops. The outer loop sets the multiplying count to the delays provided by the innermost loop, while the innermost loop is the same as above.
T-states required for innermost loop = 7 + (delay count -1) x 14 + 11
T-states required for execution of program = (multiplier count – 1) x (Tinner x 14) + 11
- For delay count = 0A H (10)10 and multipler count = 5 H then,
Tinner = 7 + (10 -1 ) x 14 + 11 = 144
- Time required for executing the program assuming operating frequency 5 MHz,
= [(5 -1) x (144 + 14) + 11] x 0.2 µsec
= 0.1286 msec
| Instruction Set of 8085 Microprocessor | |
|---|---|
| 1. | Arithmetic Instructions of 8085 |
| 2. | Data Transfer Instructions In 8085 |
| 3. | Logical Instructions in 8085 |
| 4. | Machine Control Instruction in 8085 |
