In this lecture, we are going to learn about Machine Control Instruction in 8085 in detail. We already learn the other instructions in the previous lecture, you can learn from the below link.
Also Read
| Instruction Set of 8085 Microprocessor | |
|---|---|
| 1. | Arithmetic Instructions of 8085 |
| 2. | Data Transfer Instructions In 8085 |
| 3. | Logical Instructions in 8085 |
| 4. | Machine Control Instruction in 8085 |
Machine Control Instruction in 8085
The Machine Control Instruction in 8085 includes the following instructions:
| NOP | HLT | EI |
| DI | RIM | SIM |
| IN 8-bit address | OUT 8-bit address | RST n |
NOP
| Mnemonic | NOP |
| Operation | PC = PC + 1 When this instruction is executed no operation is performed instead of that instruction. |
| No. of Bytes | 1 byte opcode of NOP |
| Machine cycles | 1 (OF) |
| Algorithm | PC ← PC + 1 |
| Flags | No flags are modified. |
| Addressing Mode | Implied Addressing Mode |
| T-states | 4 |
HLT
| Mnemonic | HLT |
| Operation | |
| No. of Bytes | 1 byte opcode of HLT |
| Machine cycles | 1 + 1 T-state (OF + 1 T-state) |
| Algorithm | |
| Flags | No flags are modified. |
| Addressing Mode | Implied Addressing Mode |
| T-states | 5 (4+1) |
| Description | When this instruction is executed, the microprocessor halts i.e. this instruction stops the microprocessor. it can be restarted by a valid interrupt or RESET signal. The registers and status flags remain unaffected. |
This instruction halts the microprocessor. it requires only the opcode fetch machine cycle. The program counter gives the memory address on the low-order and high-order address bus. The opcode of the halt instruction is read and decoded by the microprocessor. The program counter is incremented by 1 but all buses are tri-stated. now to come out of this state either a reset is required or an interrupt
EI
| Mnemonic | EI |
| Operation | IE flip-flop = 1 |
| No. of Bytes | 1 byte opcode of EI |
| Machine cycles | 1(OF) |
| Algorithm | IE flip-flop ← 1 |
| Flags | No flags are modified. |
| Addressing Mode | Implied Addressing Mode |
| T-states | 4 |
| Description | When this instruction is executed the interrupt enable flip-flop is set so that all maskable interrupts are enabled. After an interrupt is acknowledged, the interrupt enables flip-flop is reset to re-enable the interrupts. |
DI
| Mnemonic | DI |
| Operation | IE flip-flop = 0 |
| No. of Bytes | 1 byte opcode of EI |
| Machine cycles | 1(OF) |
| Algorithm | IE flip-flop ← 0 |
| Flags | No flags are modified. |
| Addressing Mode | Implied Addressing Mode |
| T-states | 4 |
| Description | When this instruction is executed the interrupt enable flip-flop is reset so that all maskable interrupts are disabled. Apart from TRAP, all other maskable interrupts can be disabled. |
RIM
| Mnemonic | RIM |
| Operation | A = status of interrupts |
| No. of Bytes | 1 byte |
| Machine cycles | 1(OF) |
| Algorithm | A ← status of interrputs and serial pate |
| Flags | No flags are modified. |
| Addressing Mode | Implied Addressing Mode |
| T-states | 4 |
| Description | When this instruction is executed the status of the interrupts is copied into the accumulator. It also reads serial data through the SID pin. |
| Example | (a) RI instruction is executed and the accumulator bit pattern is 0010 0000. The bit pattern indicates that RST 6.5 is pending interrupt. (b) RIM instruction is executed and the accumulator bit pattern is 0000 1010. Th ebit pattern indicates interrupt enable flip flop is set, RST 6.5 is masked and RST 7.5 and RST 5.5 are unmasked. |
- Bit D7 is the status of the serial port. When RIP instruction is executed the logic level of the SID pin is copied at bit D7.
- Bits D6, D5, and D4 are the status of pending interrupts. If RST 7.5 and RST 5.5 interrupt occurs the 8085 will branch to ISR of RST 7.5. As RST 5.5 is having less priority than RST 7.5, so RST 5.5 will be pending interrupt. When RIM instruction is executed the status of RST 7.5, RST 6.5, and RST 5.5 pending is copied at bits D6, D5, and D4 respectively.
- Bits D3 to D0 are the status of interrupt enable flip flop, mask 7.5, mask 6.5, and mask 5.5. When RIM instruction is executed the status of masking is loaded at bits D3 to D0.
SIM
| Mnemonic | SIM |
| Operation | |
| No. of Bytes | 1 byte |
| Machine cycles | 1(OF) |
| Algorithm | Interrupts masks and serial part ← A |
| Flags | No flags are modified. |
| Addressing Mode | Implied Addressing Mode |
| T-states | 4 |
| Description | When this instruction is executed the status of the interrupts is copied into the accumulator. It also reads serial data through the SID pin. |
| Example | To enable RST 6.5 and disable RST 7.5 and RST 5.5 the following SIM format is required. MVI A, 0DH: Load SIM format in the accumulator SIM: set the interrupt mask |
- 1-interrupt is pending/masked, 0-interrupt is not pending/masked
- SOD bit specifies serial o/p data.
- Bits D7 and D6 are serial port control. The SDE is an enable-bit used to enable/disable serial output data.
- Bit D4 is R 7.5 part of interrupt control logic. It is used to reset R 7.5 flip flop regardless of RST 7.5 masking.
- Bits D3 to Do are part of interrupt control logic. These bits are used to mask RST 5.5, RST 6.5, and RST 7.5 interrupts. The MSE bit is master control over M 7.5, M 6.5, and M 5.5 bits. If MSE = 0, the M bits have no effect, but if MSE = 1, the M bits decide to mask or unmask respective interrupts.
IN 8-bit address
| Mnemonic | IN 8-bit I/O address |
| Operation | A = (8-bit I/O address) |
| No. of Bytes | 2 byte 1st Byte: Opcode of IN 2nd byte: 8-bit address |
| Machine cycles | 3(OF + MR + IOR) |
| Algorithm | A ← (8-bit address) |
| Flags | No flags are modified. |
| Addressing Mode | Direct Addressing Mode |
| T-states | 10 (4 + 3 + 3) |
Description of IN 8-bit address instruction:
- This instruction is used to copy data from the input port address specified into the accumulator.
- When this instruction is executed the contents of the port whose address is specified are copied into the accumulator.
Example: IN 20H
- This instruction will copy the contents at the port whose address is 20 H into the accumulator
- The storing format of this IN 20 H instruction is (i) Opcode for IN and (ii) 20 H Operand (20 H is the address of the I/O device). The sequence of events occurring can be well shown by the timing diagram as shown in the figure below.
- OPCODE fetch: The program counter places address on the lower order address bus and the higher order address bus. This cycle is used to read the OPCODE of IN instruction i.e. DB H. The address for this machine cycle is given by PC. The PC is then incremented by 1.
- Memory read: The Program Counter places the address on the lower order address bus and the higher order address bus. The data byte is read from the addressed input port. The program counter is incremented by 1.
- I/O Read: In this I/O read machine cycle the address is given by a temporary register. It is an 8-bit address so the same contents are transferred on ADo-AD and As A and ALE are made high. The status of the IO/M line will be high, as it is an I/O operation. All other operations are the same as memory read operations.
OUT 8-bit address
| Mnemonic | OUT 8-bit I/O address |
| Operation | (8-bit I/O address) = A |
| No. of Bytes | 2 byte 1st Byte: Opcode of IN 2nd byte: 8-bit address |
| Machine cycles | 3(OF + MR + IOW) |
| Algorithm | (8-bit address) ← A |
| Flags | No flags are modified. |
| Addressing Mode | Direct Addressing Mode |
| T-states | 10 (4 + 3 + 3) |
Description of OUT 8-bit address instruction:
- This instruction is sued to copy the contents of the accumulator to the output port whose address is specified in the instruction.
Example: OUT 20H
- This instruction will copy the content of the accumulator to the output port whose address is 20H.
- To send data to an output device, the microprocessor sends, an 8-bit address on A0 to A7 and A8 to A15 which will be decoded and used to select one of the peripherals, with this address IOW control signal and data is required. i.e., IO/M = 1, WR = 0 and data on D0 to D7 lines.
- The storing format of OUT 20H instruction is (1) Opcode for OUT and (2) 20H operand (20H is the address of the I/O device).
- The sequence of events occurring can be well shown by the timing diagram as shown in the figure below.
- The first machine cycle is an opcode fetch which takes opcode from memory and decodes it then it comes to know that the next byte after that is an operand, so the next machine cycle will be operand fetch to take port address i.e. memory read.
- This address is stored in a temporary register and the microprocessor starts the next machine cycle i.e. I/O write.
- In this I/O write machine cycle the address is given by a temporary register.
- The only difference between I/O read and I/O write is the control signal, all other points are the same.
RST n
| Mnemonic | RST n, where n =0 to 7 |
| Operation | (SP – 1) = PCH (SP – 2) = PCL SP = SP – 2 PC = (n x 8 ) in hex |
| No. of Bytes | 1 byte opcode of RST n |
| Machine cycles | 3 (OF + MW + MW) |
| Algorithm | (SP – 1) ← PCH (SP – 2) ← PCL SP ← SP – 2 PC ← (n x 8 ) in hex |
| Flags | No flags are modified. |
| Addressing Mode | Indirect Addressing Mode |
| T-states | 12 (6 + 3 + 3) |
Description of RST n address instruction:
- This instruction transfers the program control to the specific
- memory address as shown in the table below.
- It is used as a fixed CALL instruction. These addresses are
- referred to as vector addresses
- The microprocessor multiplies the RST by 8 to estimate these vector addresses.
- Before transferring the program control to the instruction following the vector address RST instruction saves the current program counter contents on the stack like CALL instruction
- These instructions can be used as software interrupts in a program to transfer program execution to one of the 8 locations depending on which RST instruction is executed.
Example: RST 2
- This instruction is equivalent to CALL 0010, the PC contents are stored on to stack and the program sequence is transferred to address 0010 H.
- This instruction requires 3 machine cycles: opcode fetch, memory write, and memory write. The timing diagram of the RST n instruction is shown in the figure below.
Restart instructions and its locations are as per below table:
| Instructions | Location addresses |
|---|---|
| RST 0 | 0 X 8 = 0 0 0 0 H |
| RST 1 | 1 X 8 = 0 0 0 8 H |
| RST 2 | 2 X 8 = 0 0 1 0 H |
| RST 3 | 3 X 8 = 0 0 1 8 H |
| RST 4 | 4 X 8 = 0 0 2 0 H |
| RST 5 | 5 X 8 = 0 0 2 8 H |
| RST 6 | 6 X 8 = 0 0 3 0 H |
| RST 7 | 7 X 8 = 0 0 3 8 H |
- Opcode fetch: In this machine cycle the program counter places the address on the low and high order address bus. The microprocessor then reads the opcode and decodes the instruction. The opcode fetch machine cycle requires 6T states. The stack pointer is decremented by 1.
- Memory write: In this machine cycle, the stack pointer holds the low and high order address. The microprocessor writes the high-order byte of the program counter on the addressed memory location. The stack pointer is decremented by 1.
- Memory write: The stack pointer holds the low and high order address. The microprocessor writes the low-order byte of the program counter on the addressed memory location.
