# VLSI Technology MCQ For ESE

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VLSI technology MCQ, Multiple Choice Questions on VLSI topics, Gate Questions on VLSI technology, Engineering MCQ, Electronics Device & Circuit MCQ. Multiple Choice Questions and Answers on VLSI technology.

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Electronic Devices And Circuits MCQs For ESE
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## VLSI Technology MCQ For ESE

Q.1 In an integrated circuit, the SiO2 layer provides

• (a) electrical connection to an external circuit
• (b)physical strength
• (c) isolation
• (d) conducting path

Q.2 Almost all resistors are made in a monolithic integrated circuit

• (a) during the emitter diffusion
• (b) while growing the epitaxial layer
• (c) during the base diffusion
• (d) during the collector diffusion

Answer: (c) during the base diffusion

Q.3 Moor’s law relates to

• (a) speed of operation of bipolar devices
• (b) speed of operation MOS devices
• (c) the power rating of MOS devices
• (d) level of integration of MOS devices

Answer: (d) level of integration of MOS devices

Q.4 In fabricating silicon BJT in ICs by the epitaxial process, the number of diffusions used is usually

• (a) 2
• (b) 3
• (c) 4
• (d) 6

Q.5 In the fabrication of an n-p-n transistor in an IC, the buried layer on the p-type substrate is

• (a) p+-doped
• (b) n+-doped
• (c) Used to reduce the parasitic capacitance
• (d) Located in the emitter region

Q.6 The scaling factor of a MOS device is \alpha. Using the constant voltage scaling model, the gate area of the device will be scaled as

• (a) \frac{1}{\alpha}
• (b) \frac{1}{\alpha^2}
• (c) \frac{1}{\alpha^3}
• (d) \frac{1}{\alpha^4}

Q.7 Which one of the following statements is correct? In the context of IC fabrication, metallization means

• (a)connecting metallic wires
• (b) formation of interconnecting conduction patterns and boding pads
• (c) doping SiO2 layer
• (d) covering with a metallic cap

Q.8 Discussion of impurities in a semiconductor is carried out in a furnace through which a steady stream of impurity atoms is passed during the entire diffusion process. what would be the type of profile of the impurity atoms inside the semiconductor?

• (a) Linear
• (b) Gaussian
• (c) Complementary error function
• (d) Exponential

Q.9 The basic function of the buried n+ layer in an n-p-n transistor in IC is to

• (a) Reduce the magnitude of the base spreading resistance
• (b) Reduce the collector series resistance
• (c) Reduce the base width of the transistor
• (d) Increase the gain of the transistor

Answer: (b) Reduce the collector series resistance

Q.10 Which one of the statements concerning IC fabrication is not correct?

• (a) A typical wafer of doped Si may be 400um thick, of diameter 5-15 cm. The purity of the wafer does not matter and can even be polycrystalline in nature.
• (b) Resistors are obtained by utilizing the bulk resistivity of one of the regions; for example. the Ds channel of a MOSFET can act as a resistor.
• (c) Semiconductors lack magnetic properties, so they cannot exhibit inductance. However, the inductors can be realized by a combination of active and passive components.
• (d) In a reverse-biased p-n junction, the positive and negative ions exist on opposite sides of the p-n junction; because of that p-n junction behaves like a parallel plate capacitor.

Answer: (a) A typical wafer of doped Si may be 400um thick, of diameter 5-15 cm. The purity of the wafer does not matter and can even be polycrystalline in nature.

Q.11 In integrated circuits, the design of electronic circuits is based on the approach of use of

• (a) maximum number of resistors in the circuit
• (b) large sized capacitor
• (c) minimum chip area irrespective of the type of components in the design
• (d) use of only bipolar transistors

Answer: (c) minimum chip area irrespective of the type of components in the design

Q.12 why is the silicon dioxide (SiO2) layer used in ICs?

• (a) To protect the surface of the chip from external contaminants and to allow for selective formation of the n and p regions by diffusion
• (b) Because it facilitates the penetration of the desired impurity by diffusion
• (c) To control the concentration of the diffused impurities
• (d) because of its high heat conduction

Answer: (a) To protect the surface of the chip from external contaminants and to allow for selective formation of the n and p regions by diffusion

Q.13 Why is the term ‘planer technology’ for the fabrication of devices in ICs used?

• (a) The variety of manufacturing processes by which devices are fabricated, takes place through a single plane
• (b) The aluminum contacts to the collector, base, and emitter regions of the transistors in the ICs are laid in the same plane.
• (c) The collector, base, and emitter regions of the transistors in ICs are laid in the same plane
• (d) The device looks like a thin plane wafer

Answer: (a) The variety of manufacturing processes by which devices are fabricated, takes place through a single plane

Q.14 The process of extension of a single-crystal surface by growing a film in such a way that the added atoms form a continuation of the single-crystal structure is called

• (a) Ion implantation
• (b) Chemical vapor deposition
• (c) Electroplating
• (d) Epitaxy

Q.15 The maximum concentration of the element which can be dissolved in solid silicon at a given temperature is termed as

• (a) Solid solubility
• (b) Dissolution coefficient
• (c) Solidification index
• (d) Concentration index

Q.16 The biasing of an IC BJT is done by the following biasing scheme

• (a) Potential-divider biasing scheme
• (b) Fixed biasing scheme
• (c) Current mirror biasing scheme
• (d) collector to base feedback biasing scheme

Answer: (c) Current mirror biasing scheme

Q.17 The p-type epitaxial layer grown over an n-type substrate for fabricating a bipolar transistor will function as

• (a) The collector of the p-n-p transistor
• (b) The base of an n-p-n transistor
• (c) The emitter of a p-n-p transistor
• (d) The collector contact for the p-n-p transistor

Answer: (a) The collector of the p-n-p transistor

Q.18 When the photo-resist coating (during IC fabrication) is exposed to ultraviolet light photoresist becomes

• (a) oxidized
• (b) ionized
• (c) polymerized
• (d) brittle

Q.19 In VLSI n-MOS process, the thinox mask

• (a) patterns of the ion implantation within the thinox region
• (b) deposited polysilicon all over thinox region
• (c) patterns thickox regions to expose silicon where source, drain, or gate areas are required
• (d) grows thickox over thinox regions in gate areas

Answer: (c) patterns thickox regions to expose silicon where source, drain, or gate areas are required

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