8085 Microprocessor MCQ

8085 Microprocessor MCQ, Multiple Choice Questions on 8085 Microprocessor MCQ, Gate Questions on 8085 Microprocessor MCQ, Engineering MCQ, 8085 Microprocessor MCQ, 8085 Microprocessor MCQ Multiple Choice Questions. Multiple Choice Questions and Answers on 8085 Microprocessor MCQ.

Q.1 The frequency of the driving network connected between pins 1 and 2 of an 8085 chip must be

(a) equal to the desired clock frequency
(b) twice the desired clock frequency
(c) four times the desired clock frequency
(d) eight times the desired clock frequency

Answer: (b) twice the desired clock frequency

Q.2 The crystal frequency of the 8085 microprocessor is 6 MHz. The time required to execute instruction XHTL over this microprocessor

(a) 5.33 μsec
(b) 10.67 μsec
(c) 4.33 μsec
(d) 8.67 μsec

Answer: (a) 5.33 μsec

Explanation: 8085 Microprocessor internally divides the crystal frequency by 2 with the help of a flip-flop. Since the crystal frequency is given as 6 MHz.

So time period = $\frac{1}{3 \times 10^6} = \frac{10^{-6}}{3} \;sec$

Since instruction, XHTL consumes 16T states to execute an instruction.

$= \frac{16 \times 10^{-6}}{3} = 5.33\;μsec$

Q.3 The logic operation that will selectivity clear bits in register A in those positions where there are 1’s in the bits of register B is given by

(a) $A \leftarrow A + B$
(b) $A \leftarrow \bar AB$
(c) $A \leftarrow \bar A + \bar B$
(d) $A \leftarrow A \bar B$

Answer: (d) $A \leftarrow A \bar B$

Q.4 The contents of the accumulator in an 8085 microprocessor are altered after the execution of the instruction.

(a) CMP C
(b) CPI 3A
(c) ANI 5C
(d) ORA A

Answer: (c) ANI 5C

Explanation: AMP, CPI, and ORA instructions will not affect the accumulator.

ANI 5C instruction will change the content of the accumulator. (ANI is ANd operation with 8-bit immediate data).

Accumulator AND 8C → Accumulator.

Q.5 An 8085 microprocessor after the execution of the XRA A instruction

(a) The carry flag is set
(b) The accumulator contains FF_H
(c) The contents of the accumulator are shifted by one
(d) The zero flag is set

Answer:(d) The zero flag is set

Explanation: The contents of accumulator A will be 0 after XRA. So zero flag will be set. In XRA operation carry and auxiliary flagas are reset.

Q.6 Consider the following instructions for 8085 Microprocessors

MOV M, A
ADD C
MVI A, FF
CMP M

Which of these causes a change in the status of flags?

(a) 1 and 2
(b) 1, 2 and 3
(c) 3 and 4
(d) 2 and 4

Answer:(d) 2 and 4

Explanation: No flag changes in MOV and MVI instruction. All flags change in ADD and CMP as they are arithmetic instructions.

Q.7 Consider the following:

Sign Flag
Zero Flag
Carry Flag
Parity Flag

Which of the above flags of 8085 get affected by the instruction SUB B?

(a) 1 and 2
(b) 1 and 3
(c) 3 and 4
(d) 1, 2, 3 and 4

Answer:(d) 1, 2, 3 and 4

Explanation: All flags are affected by SUB B.

Q.8 Consider the following registers:

Accumulator and B register
B and C register
D and E register
H and L register

which of these 8-bit registers of the 8085 microprocessor can be paired together to make a 16-bit register?

(a) 1, 3 and 4
(b) 2, 3 and 4
(c) 1 and 2
(d) 1, 2 and 3

Answer: (b) 2, 3 and 4

Explanation: Register pairs are BC, DE, and HL

Q.9 Consider the following features in an 8085 microprocessor system with memory-mapped I/O:

I/O devices have 16-bit addresses.
I/O devices accessed using IN and OUT instructions.
There can be a maximum of 256 input devices and 256 output devices.
Arithmetic and logic operations can be directly performed with the I/O data.

Select the correct answer using the codes given below:

(a) 1, 2 and 4
(b) 1, 3 and 4
(c) 2 and 3
(d) 1 and 4

Answer: (d) 1 and 4

Explanation:

In and OUT instructions are used in the I/O mapped I/O scheme.
In memory mapped I/O scheme I/O devices limit can exceed 256.

Q.10 In the 8085 microprocessor the value of the most significant bit of the result following the execution of any arithmetic or Boolean instruction is stored in

(a) The carry status flag
(b) The auxiliary carry status flag
(c) The sign status flag
(d) The zero status flag

Answer: (c) The sign status flag

Explanation: The MSB bit represents the sign of the number. Therefore, it is stored in the sign status flag.

Q.11 The first machine cycle of an instruction is always

(a) A memory read cycle
(b) A fetch cycle
(c) An I/O rad cycle
(d) A memory write cycle

Answer: (b) A fetch cycle

Explanation: The first cycle is always the fetch cycle in any institution.

Q.12 Consider the following statements: The SIM instruction outputs the contents of the accumulator to define:

Interrupt mask bit
interrupt pending bit
serial input data line
serial output data line

Which of the statements given above are correct?

(a) 1 and 2
(b) 2 and 3
(c) 3 and 4
(d) 1 and 4

Answer: (d) 1 and 4

Explanation: SIM can mast RST 5.5, RST 6.5, and RST 7.5 and get SOD (serial output data line) pin.

Q.13 What are the number of machine cycles n, and the types of machine cycles carried out for PUSH B?

(a) n = 2, fetch and memory write
(b) n = 3, fetch and 2 memory write
(c) n = 3, fetch, memory write, and read
(d) n = 3, fetch, and 2 memory read

Answer: (b) n = 3, fetch and 2 memory write

Explanation: The machine cycle of PUSH B instruction is shown below:

The opcode fetch → 6 T-states
memory write → 3 T-state
memory write → 3 T-state

Q.14 If the 8085 microprocessor adds 87H and 79H, then

(a) both carry and zero flags will be set to 0
(b) carry flag will be set to 0 and the zero flag to 1
(c) carry flag will be set to 1 and zero flag to 0
(d) both carry and zero flags will be set to 1

Answer: (d) both carry and zero flags will be set to 1

Q.15 On the 8085 microprocessorm which of the following machine cycles are not used in CALL instruction?

Instruction fetch
I/O
memory Read
Memory write

Select the correct answer using the codes given below:

(a) 2 only
(c) 2, 3 and 4
(b) 1 and 4
(d) none of these

Answer: (a) 2 only

Explanation: machine cycles of CALL instruction are given below:

Fetch + read + Read + Write + Write

Q.16 In the 8085 Microprocessor, if the clock frequency is 5 MHz, the time required to execute an instruction of 18 T-states?

(a) 3.0 μs
(b) 3.6 μs
(c) 4.0 μs
(d) 6.0 μs

Answer: (b) 3.6 μs

Explanation: the clock frequency, f = 5 MHz

Time required to execute 1 T-state, t = 1/f

Time required to execute 18 T-states,

T = 18 t = 18 / f = 18 / 5 x 10⁶ = 3.6 μs

Q.17 Which one of the following interrupts is both level and edge-sensitive?

(a) RST 7.5
(b) RST 5.5
(c) TRAP
(d) INTR

Answer: (c) TRAP

Explanation: TRAP is level-triggered as well as edge-triggered interrupt.

Q.18 Which one of the following addressing modes is used in the instruction PUSH B?

Answer: (b) Register addressing Mode

Q.19 Which one of the following counters can be used to divide the clock frequency of a microprocessor by 5?

(a) 3-bit counter
(b) 5-bit counter
(c) Mod-3 counter
(d) Mod-5 counter

Answer: (d) Mod-5 counter

Explanation:

n-bit counter is used to divide the clock frequency by 2ⁿ.
The mod-n counter is used to divide the clock frequency by n.

Q.20 The 8085 microprocessor has two registers known as primary data pointers, These registers are:

(a) B and C
(b) D and E
(c) H and L
(d) C and D

Answer: (c) H and L

Explanation: H and L registers are known as ‘primary Data pointers’.

Q.21 READY signal in 8085 microprocessor is useful when the CPU communicates with

(a) A slow peripherals device
(b) A fast peripheral device
(c) A DMA control chip
(d) A PPI Chip

Answer: (a) A slow peripherals device

Explanation: READy signal introduces a wait state and is useful when the CPU communicates with slow peripheral devices.

Q.22 A microprocessor-based system can perform many different functions, because

(a) its operation is controlled by software
(b) It is a digital system
(c) It uses a RAM
(d) It can be controlled by input and output device

Answer: (a) its operation is controlled by software

Explanation: Microprocessor operation is controlled by software, so it can perform many different operations.

Q.23 The output data lines of microprocessors and memories are usually tri-stated, because

(a) More than one device can transmit information over that data bus by enabling only one device at a time.
(b) More than one device can transmit information over that data bus at the same time.
(c) The data lines can be multiplexed for both input and output.
(d) It increases the speed of data transfers over the data bus.

Answer: (a) More than one device can transmit information over that data bus by enabling only one device at a time.

Q.24 If the CALL instruction of 8085 in the main program is conditional then the RETURN instruction in the subroutine can be

(a) Conditional
(b) Conditional or unconditional
(c) Can be determined by DDA instruction
(d) Unconditional

Answer: (b) Conditional or unconditional

Q.25 A single instruction to clear the lower four bits of the accumulator in 8085 assembly language is

(a) XRI 0F H
(b) ANI F0 H
(c) XRI F0 H
(d) ANI 0F H

Answer: (b) ANI F0 H

Q.26 Which of the following instructions copies a byte of data into the accumulator from the memory address given in the instruction?

(a) LDA address
(b) LDAX B
(c) LHLD address
(d) STA address

Answer: (a) LDA address

Q.27 Consider a memory chip with 1024-byte storage connected to 8085 chip address lines (or any microprocessor with 16 address lines) as below. What is the range of memory address?

(a) 0000 H to 03FF H
(b) 8000 H to 83FF H
(c) F000 H to F3FF H
(d) 0000 H to FFFF H

Answer: (b) 8000 H to 83FF H

Explanation: To enable memory chip CS → LOW and is possible when output NAND gate is low. To NAND get output to be low, A₁₅ → 1 and A₁₄ to A₁₀ → 0.

So the range of memory address will be 8000 H to 83FF H.

Q.28 If the 8085 microprocessor adds 87 H and 79 H, the flags will be

(a) S = 1, Z = 0, AC = 0 and CY = 1
(b) S = 0, Z = 0, AC = 1 and CY = 0
(c) S = 1, Z = 1, AC = 1 and CY = 1
(d) S = 0, Z = 1, AC = 1 and CY = 1

Answer: (d) S = 0, Z = 1, AC = 1 and CY = 1

8085 Microprocessor MCQ

Leave a Comment Cancel reply