Diode Transistor Logic – DTL Gates

DTL stands for Diode Transistor Logic. This type of gate is built using diodes and transistors.

In this section, we are going to discuss the DTL NAND Gates and DTL NOR Gates using the DTL technology.

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DTL NAND Gate

The figure below shows the DTL NAND Gate circuit diagram of a two-input DTL positive NAND (or negative NOR) gate.

The negative bias(-V_cc) along with R₁, R₂, and R₃ will keep the transistor reverse biased.

Operation of DTL NAND Gate

1. When AB = 00, 01 or 10

• When any one or both the inputs are at logic 0 i.e. AB = 00, 01, or 10, diode D₁, D_2, or both will be conducting. This will make the potential at x, V_x = 0.7 V.

• When V_A = 0.7 V, the equivalent circuit is as shown above the figure which illustrates that the base of the transistor is at negative potential wrt emitter, so the transistor is reverse biased and the output voltage Y = 1 (HIGH).

• Thus when AB = 00, 01 or 10 output Y = 1

2. When AB = 11

• When AB = 11, both D₁ and D₂ are reverse-biased, and act as open circuits. The equivalent circuit is shown above.

• As both D₁ and D₂ are off, V_x ≠ 0.7 V but it will be much higher.

• The base of transistor Q₁ will be positive making V_BE positive.

• The transistor conducts and goes into saturation to make output Y = 0 (LOW).

• Thus when AB = 11, Y = 0

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Modified DTL NAND Gate

Large values of resistors and capacitors are difficult to fabricate economically on an integrated circuit (I_c).

Hence the DTL NAND gate of the figure shown below is modified for IC implementation by eliminating capacitor C₁, reducing the resistor values, and using dods and transistors wherever possible.

Such modified DTL NAND Gate is shown in the below figure. Note that the circuit uses a single positive supply. The modified DTL circuit, working as NAND Gate. It consists of an input stage comprising diodes D₁, D₂ and, resistor R₃ forming and AND gate. It is followed by a transistorized inverter.

Operation of Modified DTL NAND Gate

A and B are the input terminals. The input voltages A and B can be either LOW (zero volts ideally) or HIGH (+V_cc ideally).

A and B both are LOW:

• If A and B both are connected to the ground i.e. A = B = 0, then D₁ and D₂ will get forward biased, hence the potential at M us one diode voltage drop = 0.7 V. But to drive the transistor Q into conduction, we require 2.1 V to forwarded biased D₃, D₄ and the base-emitter junction of the transistor. Therefore Q is the cutoff and output

Y = V_cc = Logic 1

∴ Y = 1 (HIGH) … For A = B = 0 (LOW)

Either A or B is LOW:

• If any one of the inputs, A or B is connected to ground with either terminal connected to + V_cc, then the corresponding diode will conduct. Again V_M ≅ 0.7 V and Q will be cut off giving output Y = logic 1.

∴ Y = 1 (HIGH) … If A = 0 and B =1 or if A = 1 and B = 0

A and B both are HIGH:

• If A and B both are connected to + Vcc, then both didoes D1 and D2 will be reverse-based and do not conduct. Diodes D3 and D4 are forward biased and base current is supplied to transistor Q via Rd, D3, and D4, transistor ! is driven into saturation and the output voltage will e pulled down to a low voltage.

∴ Y = 0 (LOW) … For A = B = 1 (HIGH)

Advantages of Modified DTL NAND Gate

1. Greater fan out is possible because of the high impedance of subsequent gates in the logic 1 state.
2. It has greater noise immunity.
3. The use of diodes rather than capacitors and resistors makes the DTL circuit more economical in IC form.

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