Arithmetic Instructions of 8085

Arithmetic instructions of 8085 perform arithmetic operations such as addition, subtraction, increment, and decrement.

Addition	Any 8-bit number or the contents of a register or the contents of a memory location can be added to the contents of the accumulator and the sum is stored in the accumulator. No two other 8-bit registers can be added directly (e.g., the contents of register B cannot be added directly to the contents of register C).
Subtraction	Any 8-bit number, or the contents of a register, or the contents of a memory location can be subtracted from the contents of the accumulator and the results stored in the accumulator. The subtraction is performed in 2’s complement, and the results if negative, are expressed in 2’s complement. No two other registers can be subtracted directly.
Increment/Decrement	The 8-bit contents of a register or a memory location can be incremented or decremented by 1. Similarly, the 16-bit contents of a register pair (such as BC) can be incremented or decremented by 1. These increment and decrement operations differ from addition and subtraction in an important way; i.e., they can be performed in any one of the registers or in a memory location.

The arithmetic instructions groups include the following instructions:

1.	ADD R	2.	ADD M	3.	ADC R	4.	ADC M
5.	ADI data	6.	ACI data	7.	DAD R_p	8.	SUB R
9.	SUB M	10.	SBB R	11.	SBB M	12.	SUI data
13.	SBI data	14.	DAA	15.	INR R	16.	INR M
17.	DCR R	18.	DCR M	19.	INX R_p	20.	DCX R_p

Table of Contents

ADD R

Mnemonics	ADD R
Operation	A = A + R
No. of Byte	1 byte
Machine Cycle	1 (OF)

Algorithm	A <- A + R
Flags	All the flags are modified
Addr. Mode	Register addressing mode
T-states	4

Description	Add register R contents to the accumulator. This instruction adds the contents of register R and accumulator. The result is stored in the accumulator. The register R can be any general-purpose register like A, B, C, D, E, H, or L. In addition to the result in the accumulator, all the flags are modified to reflect the result of the operation.
Example ADD C	Let A = 47 H, C = 51 H and instruction ADD C is executed.

The examples of this instruction are:

ADD A	ADD B	ADD C	ADD D
ADD E	ADD H	ADD L

ADD M

Mnemonics	ADD M
Operation	A = A + M or A = A + (HL)
No. of Byte	1 byte
Machine Cycle	2 (OF + MR)

Algorithm	A <- A + M or A <- A + (HL)
Flags	All the flags are modified
Addr. Mode	Indirect addressing mode
T-states	4 + 3 = 7

Description	Add memory location contents to the accumulator. This instruction uses the HL register pair as a memory pointer. The contents of memory location addressed by the HL pair are added to the contents of the accumulator. The result is stored in the accumulator. To reflect the status of the result all the flags are modified. The contents of the memory location remain unchanged.
Example ADD M	Let A = 15 H, H = COH, L = 05 H, at memory location C005 :02 H is stored and the instruction ADD M is executed.

ADC R

Mnemonics	ADC R
Operation	A = A + R + CY
No. of Byte	1 byte
Machine Cycle	1 (OF)

Algorithm	A <- A + R + CY
Flags	All the flags are modified
Addr. Mode	Register addressing mode
T-states	4

Description	Add register R and carry flag contents to the accumulator. This instruction adds the contents of the specified register R to the contents of the accumulator with carry. The result is stored in the accumulator. The register R is any general-purpose register like A, B, C, D, E, H, or L.
Example ADC H A = A+H+CY	Let A = 3F H, H = 20 H, CY = 1 and the instruction ADC H is executed.

The example of this instruction are:

ADC A	ADC B	ADC C	ADC D
ADC E	ADC H	ADC L

ADC M

Mnemonics	ADC M
Operation	A = A + M + CY or A = A + (HL) + CY
No. of Byte	1 byte
Machine Cycle	2 (OF + MR)

Algorithm	A <- A + M + CY or A <- A + M + (HL)
Flags	All the flags are modified
Addr. Mode	Indirect addressing mode
T-states	4 + 3 = 7

Description	Add data in memory to the accumulator with carry. This instruction uses the HL pair as a memory pointer. The contents of the memory location addressed by the HL register pair and carry flag are added with the accumulator contents. The result is stored in the accumulator.
Example ADC M A = A+(HL)+CY	Let A = 10 H, H = CO H, L = 02 H, CY = 1 and at memory location C002: 20 H is stored, and the instruction ADC M is executed.

ADI Data

Mnemonics	ADI Data
Operation	A = A + data
No. of Byte	2 byte First Byte: Opcode Second Byte: 8-bit data
Machine Cycle	2 (OF + MR)

Algorithm	A <- A + data
Flags	All the flags are modified
Addr. Mode	Immediate addressing mode
T-states	4 + 3 = 7

Description	Add immediate 8-bit data to the accumulator. This instruction adds the 8-bit data given within the instruction to the data in the accmulator. The result is stored in the accumulator.
Example ADI B7 H	This instruction will add B7 H to the accumulator and store results in the accumulator.

ACI Data

Mnemonics	AcI Data
Operation	A = A + 8-bit data + CY
No. of Byte	2 byte First Byte: Opcode Second Byte: 8-bit data
Machine Cycle	2 (OF + MR)

Algorithm	A <- A + data + CY
Flags	All the flags are modified
Addr. Mode	Immediate addressing mode
T-states	4 + 3 = 7

Description	Add immediate 8-bit data and carry it to the accumulator. This instruction adds the 8-bit data, carry flag with the contents of the accumulator, and stores the results in the accumulator.
Example ACI 20 H	This instruction will add 8-bit data, 20H to the contents of the accumulator, and the result is stored in the accumulator.

DAD R_p

Mnemonics	DAD R_p
Operation	HL = HL + R_p
No. of Byte	1 byte
Machine Cycle	3 (OF + BI + BI)

Algorithm	HL <- HL + R_p
Flags	Only carry flag is affected. No other flags are modified to reflect the result of the operation.
Addr. Mode	Register addressing mode
T-states	4 + 3 + 3 = 10

Description

Add the specified register pair to the HL pair.
This instruction adds the contents of the specified register pair to the HL pair and stores the result in the HL pair.
The register pair R is a 16-bit register pair like BC, DE, HL, or stack pointer.
Only a higher order register is to be specified for the register pair within the instruction.
Only the carry flag is modified to reflect the status of the result.

Example

DAD D

This is a one-byte instruction.
The operation is 16-bit addition. But as 8085 is an 8-bit processor, it requires additional time to complete the instruction execution.
At that time 8085 is busy in execution so it enters the bus idle machine cycle.
During the bus idle machine cycle, no operation on the bus was performed.
The fetching of the next instruction is stopped by not giving control signals RD and ALE. PC is not incremented by 1.
In all total 3 machine cycles required:
- (1) OPCODE fetch
- (2) Bus idle machine cycle
- (3) Bus idle machine cycle.
OPCODE fetch: The program counter places address on the lower order address bus and the higher order address bus. The address for this machine cycle is given by PC. The PC is then incremented by 1.
Bus Idle cycles: This machine cycle is required to perform internal operation i.e.16-bit addition. During these machine cycles the buses are not in use.
The examples of this instrction are:

DAD B

DAD D

DAD H

DAD SP

SUB R

Mnemonics	SUB R
Operation	A = A – R
No. of Byte	1 byte
Machine Cycle	1 (OF)

Algorithm	A <- A – R
Flags	All flags are modified to reflect the result of the operation.
Addr. Mode	Register addressing mode
T-states	4

Description

Subtract register from the accumulator
This instruction subtracts the contents of the specified register from the contents of the accumulator and the result is stored in the accumulator.
The contents of the registers R are not altered.
The register R can be any general-purpose register like A, B, C, D, E, H, or L.
Note: The subtraction is performed by using 2's complement method. 2's complement is done by the microprocessor itself. The programmer only specifies the two data bytes.

Example
SUB B

Let A = 37H, B = 40H and the instruction SUB B is executed.
B = 0100 0000
2’s complement of B = 1100 0000