8259 Programmable Interrupt Controller

🧠 Introduction: What is 8259A Programmable Interrupt Controller?

The Intel 8259 Programmable Interrupt Controller (PIC) is used to manage hardware interrupts in microprocessor-based systems. It’s a key part of traditional x86 architecture and helps prioritize multiple interrupt requests (IRQs) before passing them to the CPU.

In a system with many I/O devices, the CPU needs a way to handle interrupts efficiently. The 8259A PIC reduces the complexity by combining multiple interrupt lines into a single interrupt output (INT).

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🔧 8259 Features at a Glance

• It is an LSI chip that manages 8 levels of interrupts, i.e., it is used to implement 8 8-level interrupt system.
• It can be cascaded in a master-slave configuration to handle up to 64 levels of interrupts.
• It can identify the interrupting device.
• It can resolve the priority of interrupt requests, i.e., it does not require any extra
• It can be operated in various priority modes, such as fixed priority and rotating priority.
• The interrupt requests are individually maskable.
• It provides an 8-bit vector number as interrupt information.
• It does not require a clock signal.
• It can be used in polled as well as interrupt modes.
• The starting address of the vector number is programmable.
• It can be used in buffered mode. (Buffered mode is applicable for multiprocessor systems).

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Also Read: 8237 DMA Controller

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Block Diagram of 8259 Programmable Interrupt Controller

The block diagram of the 8259 is shown in the figure below. It contains the following blocks:

• Data Bus Buffer: It is used to transfer data between the microprocessor and the internal bus.

• Read/Write control logic: It sets the direction of the data bus buffer. It controls all internal read/write operations. It contains initialization and operation command registers.

• Cascaded buffer and comparator: In master mode, it functions as a cascaded buffer. The cascaded buffer outputs a slave identification number on cascade lines. In slave mode, it functions as a comparator. The comparator reads slave identification numbers from cascade lines and compares these numbers with its internal identification number. In buffered mode, it generates an EN signal.

• Control Logic: It generates an INT signal. In response to the INTA signal, it releases a three-byte CALL address or a one-byte vector number. It controls read/write control logic, cascade buffer/comparator, in-service register, priority resolver, and IRR.

• Interrupt request register (IRR): It is used to store all pending interrupt requests. Each bit of this register s set at the rising edge or at the high level of the corresponding interrupt request line. The microprocessor can read the contents of this register by issuing appropriate command words.

• In-service register (InRR): It is used to store all interrupt levels currently being serviced. Each bit of this register is set by the priority resolver and reset by the End of the interrupt command word. The microprocessor can read the contents of this register by issuing appropriate command words.

• Priority resolver: It determines the priorities of the bits set in the IRR. To make a decision, the priority resolver looks at the ISR. If the higher priority bit in the InSR is set, then it ignores the new request. If the priority resolver finds that the new interrupt has a higher priority than the highest priority interrupts currently being serviced and the new interrupt is not in service, then it will set the appropriate bit in the InSR and send the INT signal to the interrupt request.

• Interrupt mask register (IMR): It is a programmable register. It is used to mask unwanted interrupt requests by writing appropriate command words. The microprocessor can read the contents of this register without issuing any command word.

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Pin Configuration of 8259 Programmable Interrupt Controller

The pin configuration of the 8259 PIC (Programmable Interrupt Controller) is as shown in the figure below:

Symbol	Description
D0-D7	It is an active low-control input line. It is used to write data into registers. it is connected to \overline{IOWR} or \overline{MEMWR} of the system bus.
\overline{RD}	It is an active low-control input line. It is used to read the contents of the internal registers. It is connected to \overline{IOR} or \overline{MEMR} of the system bus.
\overline{WR}	It is an interrupt acknowledge input line. This signal is generated by the microprocessor. The 8259A accepts two \overline{INTA} pulses to release a one-byte vector number. The 8259 A does not work without \overline{INTA} pulses in vectored mode.
A0	It is an address input line. It is used to select the appropriate control register. It is connected to one of the address lines of the system address bus.
\overline{CS}	It is an active low-chip select input line. It is used to select the 8259 A chip. This signal is generated by the address decoder.
CAS0-CAS2	These are bi-directional 3-bit cascade lines. These lines are used in cascade mode only. In master mode, these lines function as output lines. In this mode, the pIC places a 3-bit slave identification number on cascade lines.
\overline{SP}/ \overline{EN}	It is an active, low bi-directional control line. In nonbuffered mode, it functions as \overline{SP} input line. In this mode, \overline{SP} is used to distinguish between master and slave PICs. In buffered mode, it functions as an \overline{EN} output line. In this mode, it is used to enable data buffers.
INT	It is an interrupt output line. it goes high whenever a valid interrupt request is activated. It must be connected to the INTR input of the microprocessor.
\overline{INTA}	It is an interrupt acknowledge input line. This signal is generated by the microprocessor. The 8259A accepts two \overline{INTA} pulses to release a one-byte vector number. The 8259 A does not work without \overline{INTA} pulses in vectored mode.
IR0-IR7	These are asynchronous interrupt request input lines. These signals are generated by peripherals. They can be used in either edge-triggered or level-triggered mode. The IR input should make low to low-to-high transition at n levels as well as an edge-triggered mode.

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Also Read: 8255 PPI (Programmable Peripheral Interface)

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Priority Modes of the 8259 Programmable Interrupt Controller

The various priority modes of the 8259 are:

1. Fully nested mode
2. Special fully nested mode
3. Rorating Priority mode
   • The rotating priority mode can be set as:
     1. Automatic rotation
     2. Specific rotation
4. Special masked Mode

Operating Modes of 8259 Programmable Interrupt Controller

8259 has two operating modes:

1. Interrupt drive: In this mode, the 8259 Interrupts the processor with the INT pin whenever it gets an interrupt.
2. Polled Mode: In this mode, the INT output is not used. The microprocessor checks the status of the interrupt request by issuing the poll command.

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🛠️ Internal Blocks of 8259A

• IRR (Interrupt Request Register): Tracks pending interrupts.
• IMR (Interrupt Mask Register): Masks (disables) specific interrupts.
• ISR (In-Service Register): Shows which interrupt is currently being serviced.
• Priority Resolver: Decides which interrupt to serve first.
• Control Logic: Manages communication with CPU.

🧠 These blocks work together to determine which interrupt is valid, active, or masked.

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🔄 Cascading Multiple 8259 PICs (Master-Slave)

You can cascade up to 8 slave 8259A chips with a master to support 64 interrupts.

• Master’s IR lines are connected to slave INT outputs
• Only one chip responds to INTA at a time

🧩 This is used in PC/AT architecture, where IRQs 8–15 are handled by a second (slave) 8259.

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🔢 Programming 8259A PIC: Initialization Example

Here’s how to initialize 8259A using assembly language for the 8086 CPU:

; ICW1: Edge triggered, cascade mode, expect ICW4
MOV AL, 0x11
OUT 0x20, AL

; ICW2: Interrupt vector address (e.g. 0x20 = IRQ0)
MOV AL, 0x20
OUT 0x21, AL

; ICW3: IR2 has slave 8259
MOV AL, 0x04
OUT 0x21, AL

; ICW4: 8086/88 mode, normal EOI
MOV AL, 0x01
OUT 0x21, AL

✔️ You can now mask or unmask individual interrupts using OCW1:

; Mask all except IR0 (Timer)
MOV AL, 0xFE
OUT 0x21, AL

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📊 Comparison: 8259A vs Modern APIC

Feature	8259A	APIC
Interrupts	Up to 64	256+
Priority Handling	Static & rotating	Dynamic
System	Legacy x86	Modern multi-core CPUs
Protocol	Edge/Level	Message-Signaled Interrupts (MSI)

🔁 In modern PCs, the 8259A is replaced by Advanced Programmable Interrupt Controllers (APICs), but it remains essential in embedded systems and learning.

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🧠 Real-Life Use Case of 8259A

In older PCs, the system timer, keyboard, floppy disk, and COM ports were all connected via the 8259 PIC.

Example:

• IRQ0: Timer
• IRQ1: Keyboard
• IRQ4: COM1
• IRQ6: Floppy Disk Controller

⏱ When a device signals an interrupt, the PIC prioritizes it and sends an interrupt signal (INT) to the CPU.

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FAQs on 8259 Programmable Interrupt Controller

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🧭 Conclusion

The 8259A Programmable Interrupt Controller plays a vital role in traditional microprocessor systems. By offloading interrupt management from the CPU, it makes systems more efficient and responsive. Understanding its architecture, initialization, and cascading is a must for every embedded systems engineer or computer science student.

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