In this lecture, we will learn about the Logical Instructions in 8085 used for programming. We will learn all the logical instructions with a very detailed analysis. So before starting each instruction, we will know what logical instructions are available in the 8085 microprocessor.
So let’s start with the group of instructions and its name below.
Also Read:
Logical Instructions in 8085
In the 8085 microprocessor, logical instructions perform various logical operations with the content of the accumulator.
| AND, OR, XOR | Any 8-bit number, or the contents of a register or of a memory location can be logically ANDed, ORed, or XORed with the content of the accumulator. The results are stored in the accumulator. |
| Rotate | Each bit in the accumulator can be shifted either left or right to the next position. |
| Compare | Any 8-bit number, or the content of a register, or a memory location can be compared for equally, greater than, or less than, with the contents of the accumulator. |
| Complement | The contents of the accumulator can be complemented. All 0s are replaced by 1s and all 1s are replaced by 0s. |
The logical instructions of 8085 include the following instructions:
| ANA R | ANA M | ANI data | ORA R |
| ORA M | ORA data | XRA R | XRA M |
| XRI data | CMA | CMC | STC |
| CMP R | CMP M | CPI data | RLC |
| RRC | RAL | RAR |
Now we will discuss each logical instruction of 8085 in detail.
ANA R
| Mnemonic | ANA R |
| Operation | A = A AND R |
| No. of Bytes | 1 byte |
| Machine cycles | 1 (OF) |
| Algorithm | A ← A ∧ R |
| Flags | S, Z, and P are modified to reflect the result of the operation. The carry flag is reset and the AC flag is set. |
| Addressing Mode | Register addressing mode |
| T-states | 4 |
| Description | Logically AND register with accumulator. This instruction will logically AND the contents of the specified register with the contents of the accumulator and the result will be stored in the accumulator. The operation of ANDing is performed bit by bit. i.e. B0 bit of the accumulator is ANDed with the B0 bit of the specified register, and so on up to the B7 bit of the accumulator is ANDed with the B7 bit of the specified register. |
| Example ANA B | Let A = 65 H and B = 82 H and instruction ANA B is executed. |
The example of intruction ANA R are:
| ANA A | ANA B | ANA C | ANA D |
| ANA E | ANA H | ANA L |
ANA M
| Mnemonic | ANA M |
| Operation | A = A AND M |
| No. of Bytes | 1 byte |
| Machine cycles | 2 (OF + MR) |
| Algorithm | A ← A ∧ M |
| Flags | S, Z, and P are modified to reflect the result of ANDing. The carry flag is reset and the AC flag is set. |
| Addressing Mode | Indirect addressing mode |
| T-states | 7 (4 + 3) |
| Description | Logically AND memory with accumulator. The contents of the memory location pointed by the HL register pair are ANDed with the contents of the accumulator and the result is stored in the accumulator. The HL register pair acts as a memory pointer. |
| Example ANA M | Let A = 4A H, H = 20 H, L = FF H, at memory location 20FF : EF H is stored and instruction ANA M is executed. |
ANI Data
| Mnemonic | ANI Data |
| Operation | A = A AND data |
| No. of Bytes | 2 bytes 1st Byte: Opcode 2nd Byte: 8-bit data |
| Machine cycles | 1 (OF +MR) |
| Algorithm | A ← A ∧ Data |
| Flags | S, Z, and P are modified to reflect the result of the operation. CY is reset and AC is set. |
| Addressing Mode | Immediate Addressing mode |
| T-states | 7 (4+3) |
| Description | Logically AND immediate data with accumulator. This instruction logically ANDs the content of the accumulator with the 8-bit data specified in the instruction. The result is stored in the accumulator. The ANDing is done bitwise. |
| Example ANI 0FH | Let A = F7 and instruction ANI OF is executed. |
ORA R
| Mnemonic | ORA R |
| Operation | A = A OR R |
| No. of Bytes | 1 byte |
| Machine cycles | 1 (OF) |
| Algorithm | A ← A ∨ R |
| Flags | S, Z, and P are modified to reflect the result of the operation. AC and CY are reset |
| Addressing Mode | Register Addressing mode |
| T-states | 4 |
| Description | Logically OR contents of specified register with accumulator. This instruction will logically OR the contents of the specified register with the accumulator and the result is stored in the accumulator. The ORing is done bit by bit. i.e. B0 bit of register with B0 bit of accumulator, B1 bit of register with B1 bit of register with b1 bit of accumulator, and so on up to B7 bit. The register R can be any general-purpose register like A, B, C, D, E H, or L. |
| Example ORA C | Let A = A2 H and C = B5 H and instruction ORA C are executed. |
The examples of the instruction ORA R are:
| ORA A | ORA B | ORA C | ORA D |
| ORA E | ORA H | ORA L |
ORA M
| Mnemonic | ORA M |
| Operation | A = A OR M |
| No. of Bytes | 1 byte |
| Machine cycles | 2 (OF + MR) |
| Algorithm | A ← A ∨ M or A ← A ∨ (HL) |
| Flags | S, Z, and P are modified to reflect the result of the operation. AC and CY are reset |
| Addressing Mode | Indirect Addressing mode |
| T-states | 7 (4+3) |
| Description | Logically OR contents of memory with accumulator. This instruction will logically OR the contents of the accumulator with the contents of the memory location and the result is stored in the accumulator. The address of the memory location is given by the HL register pair. The ORing operation is done bitwise. |
| Example ORA M | Let A = AA H, H = AA H, L = ABH, at memory location AAAB: 55H data stored, and the instruction ORA M is executed. |
ORI Data
| Mnemonic | ORI Data |
| Operation | A = A OR Data |
| No. of Bytes | 2 byte |
| Machine cycles | 2 (OF + MR) |
| Algorithm | A ← A ∨ Data |
| Flags | S, Z, and P are modified to reflect the result of the operation. AC and CY are reset |
| Addressing Mode | Immediate Addressing mode |
| T-states | 7 (4+ 3) |
| Description | Logically OR immediate data with accumulator. The contents of the accumulator are ORed with 8-bit data specified along with the instruction and the result is stored in the accumulator. |
| Example ORI 20H | Let A = 55 and instruction ORI 20 H is executed. |
XRA R
| Mnemonic | XRA R |
| Operation | A = A ⊕ R |
| No. of Bytes | 1 byte |
| Machine cycles | 1 (OF) |
| Algorithm | A ← A XOR R or A ← A ⊕ R |
| Flags | S, Z, and P are modified to reflect the result of the operation. AC and CY are reset |
| Addressing Mode | Register Addressing mode |
| T-states | 4 |
| Description | XOR register with accumulator. This instruction will XOR the content of the accumulator with the content of the register specified and the result will be stored in the accumulator. The XORing operation is done bit by bit. i.e. B0 bit of the register is XORed with the B0 bit of the accumulator and so on. R may be any general-purpose register like A, B, C, D, E, H, and L. |
| Example XRA D | Let A =77H and D = 06H and instruction XRA D is executed. |
XRA M
| Mnemonic | XRA M |
| Operation | A = A ⊕ M |
| No. of Bytes | 1 byte |
| Machine cycles | 2 (OF + MR) |
| Algorithm | A ← A XOR M or A ← A ⊕ M |
| Flags | S, Z, and P are modified to reflect the result of the operation. AC and CY are reset |
| Addressing Mode | Indirect Addressing mode |
| T-states | 7 (4+3) |
| Description | Logically XOR data is in memory with an accumulator. This instruction will logically XOR the content of the memory location with the contents of the accumulator and the result is stored in the accumulator. the HL register pair give the address of the memory location. The operation of XORing is performed bitwise. |
| Example XRA M | Let A =A5 H, H = 50 H, L = 05 H, at memory location 5005: 50H is sorted, and the instruction XRA M is executed. |
XRI Data
| Mnemonic | XRI Data |
| Operation | A = A ⊕ data |
| No. of Bytes | 2 byte 1st Byte: Opcode 2nd byte: 8-bit data |
| Machine cycles | 2 (OF + MR) |
| Algorithm | A ← A XOR data or A ← A ⊕ data |
| Flags | S, Z, and P are modified to reflect the result of the operation. AC and CY are reset |
| Addressing Mode | Immediate Addressing mode |
| T-states | 7 (4+3) |
| Description | Logically XOR immediate data with an accumulator. This instruction will logically XOR the contents of the accumulator with the 8-bit data specified along the instruction. The result is stored in the accumulator. The XORing operation is done bitwise. |
| Example XRI 2FH | This instruction will XOR the contents of the accumulator with data 2F H and the result will be stored in the accumulator. |
CMA
| Mnemonic | CMA |
| Operation | A =  |
| No. of Bytes | 1 byte |
| Machine cycles | 1 (OF) |
| Algorithm | A ← |
| Flags | No flags are modified |
| Addressing Mode | Implied addressing mode |
| T-states | 4 |
| Description | Complement accumulator. This instruction complements the content of the accumulator and the result is placed in the accumulator. The complement is performing an inversion operation of each bit i.e. 0 will be replaced by 1 and 1 will be replaced by 0. |
| Example CMA | If A = ABH and the instruction CMA is executed. After the CMA instruction is executed A will contain 54H and there will be no change in the flag status. |
CMC
| Mnemonic | CMC |
| Operation | CY = |
| No. of Bytes | 1 byte |
| Machine cycles | 1 (OF) |
| Algorithm | CY ← |
| Flags | Only the carry flag is complemented. No other flags are affected. |
| Addressing Mode | Implied addressing mode |
| T-states | 4 |
| Description | Complemented the carry flag. This instruction complements the carry flag. i.e. if the carry flag = 1 the instruction will reset it and if CY flag = 0 the instruction will be set to 1. |
| Example CMC |  |
STC
| Mnemonic | STC |
| Operation | CY = 1 |
| No. of Bytes | 1 byte |
| Machine cycles | 1 (OF) |
| Algorithm | CY ← 1 |
| Flags | Only the carry flag is set. No other flags are modified. |
| Addressing Mode | Implied addressing mode |
| T-states | 4 |
| Description | Set the carry flag. This instruction sets the carry flag. |
| Example CMC |  |
CMP R
| Mnemonic | CMP R |
| Operation | (A – R) A compare R |
| No. of Bytes | 1 byte |
| Machine cycles | 1 (OF) |
| Algorithm | A Compare R |
| Flags | S, Z, and P are modified to reflect the status of subtraction, and Z, CY are used to indicate the result of comparison. |
| Addressing Mode | Register addressing mode |
| T-states | 4 |
| Description | Compare register with accumulator. This instruction compares the contents of the accumulator with the content of the register specified. The operation of comparing is performed by subtracting the register contents from the accumulator contents. The contents of the register or accumulator are not altered. The result of the comparison is indicated by setting the flags as follows: If A > R : CY = 0 and Z = 0 If A = R : Cy = 0 and Z = 1 If A < R : CY = 1 and Z = 0 The S, P, and AC flags are modified to reflect the status of subtraction, or Z, and CY are used to indicate the result of the comparison. The register R is any general-purpose register like A, B, C, D, E, H, or L. |
| Example 1. CMP B 2. CMP C 3. CMP D | 1. Let A = 20H, B = 10H. Now if the instruction CMP B is executed. Then the status of flags will be CY = 0 and Z = 0 to indicate A > B. 2. Let A = 10H, C = 10H. Now if the instruction CMP C is executed. Then the status of flags will be CY = 0 and Z = 1 to indicate A = B. 3. Let A = 10H, D = 20H. Now if the instruction CMP D is executed. Then the status of flags will be CY = 1 and Z = 0 to indicate A < B. |
The examples of the instruction CMP R are:
| CMP A | CMP B | CMP C | CMP D |
| CMP E | CMP H | CMP L |
CMP M
| Mnemonic | CMP M |
| Operation | (A – M) |
| No. of Bytes | 1 byte |
| Machine cycles | 2 (OF + MR) |
| Algorithm | A Compare M |
| Flags | Z and CY flags are used to indicate the result of the comparison. S, P AC flags are modified to reflect the status of subtraction. |
| Addressing Mode | Indirect addressing mode |
| T-states | 7 ( 4+3) |
| Description | Compare memory with accumulator. This instruction compares the contents of the accumulator and memory location contents. The HL register pair gives the address of the memory location. The contents of the accumulator and memory location are not altered. The result of the comparison is indicated by setting the flags as follows: If A > M : CY = 0 and Z = 0 If A = M : Cy = 0 and Z = 1 If A < M : CY = 1 and Z = 0 The S, P, and AC flags are modified to reflect the status of subtraction, or Z, and CY are used to indicate the result of the comparison. |
| Example CMP M | Let A = 20H, H = C0H, L = 02H at memory location C002: 10H is stored, and the instruction CMP M is executed. The flag staus will be as follows: CY = 0, Z = 0, P = 0 S = 0, AC = 0 |
CPI Data
| Mnemonic | CPI Data |
| Operation | (A – data) |
| No. of Bytes | 2 byte 1st byte: Opcode 2nd byte: 8-bit data |
| Machine cycles | 2 (OF + MR) |
| Algorithm | A Compare data |
| Flags | Z and CY flags are used to indicate the result of the comparison. S, P AC flags are modified to reflect the status of subtraction. |
| Addressing Mode | Immediate addressing mode |
| T-states | 7 ( 4+3) |
| Description | Compare immediate data with the accumulator. This instruction subtracts the 8-bit data given in the instruction from the content of the accumulator and sets the condition flags as a result of subtraction. If sets the zero flag if A = data and sets the carry flag if A < data. The contents of the accumulator and data are unchanged, as the result of comparison is indicated by the flags. |
| Example CPI 30H | Let A = 10H and the instruction CPI 30H is executed. The flag staus will be as follows: CY = 1, Z = 0, P = 0 S = 1, AC = 0 |
RLC
| Mnemonic | RLC |
| Operation | For n = 0 to 6, Bn+1 = Bn B0 = CY = B7 |
| No. of Bytes | 1 byte |
| Machine cycles | 1 (OF ) |
| Algorithm | Bn+1 ← Bn (for n = 0 to 6) B0 ← B7 CY ← B7 |
| Flags | Only the carry flag is modified. Bit B7 is copied to the carry flag. no other flags are modified. |
| Addressing Mode | Implied addressing mode |
| T-states | 4 |
| Description | Rotate Accumulator left. This instruction will rotate the content of the accumulator to the left by 1 bit. i.e. it shifts the bits left by one position. B0 will be transferred to B1, b1 to B2, and so on B6 to b7, B7 to B0 as well as the carry flag. The operation is shown in the figure below.  |
| Example | Let A = 1F H and instruction RLC is executed. the content of the accumulator will be rotated by 1 bit to the left and the result will be stored in the accumulator i.e. A = 3E H |
RRC
| Mnemonic | RRC |
| Operation | For n = 0 to 6, Bn = Bn+1 B7 = CY = B0 |
| No. of Bytes | 1 byte |
| Machine cycles | 1 (OF ) |
| Algorithm | Bn ← Bn+1 (for n = 0 to 6) B7 ← B0 CY ← B0 |
| Flags | Only the carry flag is modified. All other flags are unmodified. |
| Addressing Mode | Implied addressing mode |
| T-states | 4 |
| Description | Rotate Accumulator Right. This instruction rotates the contents of the accumulator to the right by one position. Bit B0 is placed in B7 as well as CY flag as shown in the figure below.  |
| Example A = 1CH and CY = 1 | After the execution of the instruction, the accumulator contents will be 0E H and the carry flag will be reset. |
RAL
| Mnemonic | RAL |
| Operation | For n = 0 to 6, Bn+1 = Bn CY = B7 B0 = CY |
| No. of Bytes | 1 byte |
| Machine cycles | 1 (OF ) |
| Algorithm | Bn+1 ← Bn (for n = 0 to 6) CY ← B7 B0 ← CY |
| Flags | Only the carry flag is modified. All other flags are unmodified. |
| Addressing Mode | Implied addressing mode |
| T-states | 4 |
| Description | Rotate Accumulator left through Carry. This instruction will rotate the content of the accumulator to the left by 1-bit position along with carry. B7 is placed in CY and CY is placed in bit B0. The below figure shows the operation.  |
| Example | Let A = 0EH, CY =1. After execution of the instruction, the contents of the accumulator will be 1DH ad CY = 0. |
RAR
| Mnemonic | RAR |
| Operation | For n = 0 to 6, Bn = Bn+1 B7 = CY CY = B0 |
| No. of Bytes | 1 byte |
| Machine cycles | 1 (OF ) |
| Algorithm | Bn ← Bn+1 (for n = 0 to 6) CY ← B0 B7 ← CY |
| Flags | Only the carry flag is modified. All other flags are unmodified. |
| Addressing Mode | Implied addressing mode |
| T-states | 4 |
| Description | Rotate Accumulator Right through Carry. This instruction will rotate the content of the accumulator right by 1-bit position along with carry. B0 is placed in CY and CY is placed in bit B7. The below figure shows the operation.  |
| Example | Let A = 0EH and CY = 1 and the instruction RAR is executed. After execution of the instruction accumulator contents will be (1000 0111) 87H and the carry flag will be reset. |
