Interrupts in 8085 Microprocessor

Whenever more than one I/O device is connected to a microprocessor-based system, any one of the I/O devices may ask for service at any time. There are two methods by which the microprocessor can service these I/O devices.

1. Polling Routine
2. Interrupts

Basic Definitions of Interrupts

1. Interrupts: It is a mechanism by which an I/O device ( hardware interrupts) or an instruction (software interrupts) can suspend the normal execution of the processor and get itself serviced.
2. Interrupt Service routine (ISR): A small program or a routine that when executed services the corresponding interrupting source is called an ISR.
3. Vectored/Non-vectored Interrupts: If the ISR address of an interrupt is to be taken from the interrupting source itself, it is called a non-vectored interrupt, else it is a vectored interrupt.
4. Maskable/Non-maskable Interrupt: In cases where an interrupt is masked, the microprocessor will not respond to the interrupt even is the interrupt is activated. The interrupt which can be masked under the software control is called as maskable Interrupt. The interrupts which cannot be masked under the software control are called non-maskable interrupts.

Types of Interrupts in 8085

There are two types of interrupts in the 8085 microprocessor. They are:

1. Hardware Interrupts:
   • The peripheral device activates the interrupt by activating the respective pin.
   • In response to the interrupting request, the microprocessor completes the current instruction execution in the main program and transfers program control to the interrupt service routine.
   • In the ISR routine, the task is completed. The task may be to read data, write data, upload the status, update the counter, etc.
   • After completing the task, the program control is transferred back to the main program.
   • These types of interrupts where the microprocessor pins are used to receive interrupt requests are called Hardware Interrupts.
   • The 8085 Microprocessor has five hardware interrupts.
     1. TRAP
     2. RST 7.5
     3. RST 6.5
     4. RST 5.5
     5. INTR
2. Software Interrupts:
   • In the case of software interrupts, the cause of the interrupt is the execution of the instruction.
   • The 8085 microprocessor has eight instructions. These eight instructions are RST 0 to RST 7.
   • Such interrupts are called software interrupts.
   • They allow microprocessors to transfer program control from the main program to the subroutine program.
   • After completing the subroutine program. the program control returns back to the main program.

Also Read: Instruction Set of 8085 Microprocessor

Hardware Interrupts in 8085

1. TRAP :

• It is a non-maskable, edge and level-triggered interrupt.
• It is unaffected by any mask or interrupt enable.
• The TRAP signal must make a LOW to HIGH transition and remain HIGH until acknowledge. This avoids false triggering due to noise or glitches.
• It has the highest priority among all interrupts.
• This interrupt transfers the microprocessor’s control to location 0024H.
• Application: It is used for emergency purposes like power failure, parity error checker, smoke detector, etc.

2. RST 7.5 :

• It is a maskable, edge-triggered interrupt request input line. This interrupt is triggered at the rising edge of the signal.
• It has the highest priority among all maskable interrupts and the second priority among all interrupts.
• The interrupt vector location for this interrupt is 003CH.

3. RST 6.5 and RST 5.5 :

• These are level-triggered, maskable interrupt request input lines.
• RST 6.5 transfer the microprocessor’s control to location 0034H while RST 5.5 transfer the microprocessor’s control to location 002CH.

4. INTR :

• It is a level triggered, maskable interrupt request input line.
• This interrupt works in conjunction with RST N or CALL instruction.
• The INTR logic consists of an INTE flip-flop, OR gate, and inverter. The INTR pin is logically ANDed with the output of the INTE flip-flop.

Interrupt Vector Location

Interrupt Type	ISR address (Vector Location)	Trigger	Priority	Maskable	Vectored
TRAP	0024 H	Edge and Level	1st (Highest)	NO	YES
RST 7.5	003C H	Level	2nd	YES	YES
RST 6.5	0034 H	Level	3rd	YES	YES
RST 5.5	002C H	Level	4th	YES	YES
INTR	No specific location	Level	5th (Lowest)	YES	NO

Software Interrupts in 8085

• The 8085 microprocessor has eight instructions from RST 0 to RST 7.
• These instructions allow the transfer of program control from the main program to predefined service routine addresses.
• A predefined service routine is also referred to as ISR.
• After completing the ISR program control is transferred back to the main program.
• 8085 microprocessor provides eight software interrupts RST 0 to RST 7; These instructions are used to call interrupt service routine.
• Format of RST N Instruction OPCODE is as follows:

D7	D6	D5	D4	D3	D2	D1	D0
1	1	N2	N1	N0	1	1	1

• The vector locations, for RST N instruction, are as follows:

Instruction	Address of ISR
RST 0	0000H (8 X 0 ) = 0000H
RTS 1	0008H (8 X 1 ) = 0008H
RST 2	0010H (8 X 2 ) = 0010H
RST 3	0018H (8 X 3 ) = 0018H
RST 4	0020H (8 X 4 ) = 0020H
RST 5	0028H (8 X 5 ) = 0028H
RST 6	0030H (8 X 6 ) = 0030H
RST 7	0038H (8 X 7 ) = 0038H

• The difference between two successive locations is only 8 bytes. Hence jump instructions must be stored in the corresponding location to transfer the microprocessors’ control to the user-defined ISR address.
• Software interrupts are not used to handle asynchronous events. They are used to call software routines like single steps, breakpoints, etc.

Comparison of Hardware interrupts and Software interrupts

Sr. No	Software Interrupt	Hardware Interrupt
1.	It is a synchronous event.	It is an asynchronous event.
2.	This interrupt is requested by executing instruction.	This interrupt is requested by an external device on a pin.
3.	PC in incremented.	PC is not incremented.
4.	The microprocessor does not execute any interrupt acknowledge cycle to acknowledge this interrupt. The microprocessor executes a normal instruction cycle.	The microprocessor executes either interrupt acknowledge cycle bus or idle machine cycle to acknowledge this interrupt.
5.	It cannot be ignored or masked.	It can be masked except for TRAP.
6.	It has the highest priority among all interrupts.	The priority is lower than that of a software interrupt.
7.	It does not affect interrupt control logic.	It affects interrupt control logic.
8.	It is not used to interface peripherals that means it does not improve the throughput of the system. It is used in program debugging.	It is used to interface peripherals in interrupt-driven I/O. It improves the throughput of the system.

Masking or unmasking of Interrupts in 8085

For masking/unmasking of interrupts, there are four instructions:

1. EI
2. DI
3. RIM
4. SIM

1. EI : Enable Interrupt

• This instruction s used to enable all maskable interrupts. i.e interrupts RST 7.5, RST 6.5, RST 5.5 and INTR can be enabled/activated using the EI instruction.
• Whenever an interrupt is acknowledged, the interrupt enable flip-flop will reset and all the interrupts ae disabled.
• If the interrupts are to be enabled, then the EI instruction is to be executed within the ISR.

2. DI : Disable Interrupt

• This instruction resets the interrupt enable flip-flop i.e it can be used to disable RST 7.5, RST 6.5, RST 5.5 and INTR interrupts.

3. SIM : Set Interrupt Mask

• This instrction is used to enable/disable the RST 7.5, RST 6.5 and RST 5.5 interrupts.
• This instruction does not affect on the TRAP and INTR inputs.
• It ccan also be used for serial data transmission.
• It transfer the control word from accumulator to the interrupt control logic, and the serial control logic.
• So, it is essential to load the control word into the accumulator before the xecution of SIM instruction.

• Bits D7 and D6 are serial port control. The SDE is enable bit used to enable/disable serial output data. If D6 bit is enables, D7 bit is transferred to SOD pin.
• Bit D4 is R 7.5 part of interrupt control logic. It is used to reset R 7.5 flip-flop regardless of RST 7.5 masking.
• Bits D3 and D0 are partof interrupt control logic. These bits are used to mask RST 5.5, RST 6.5 and RST 7.5 interupts.
• The MSE bit is master control over M 7.5, M 6.5 abd M 5.5 bits. If MSE = 0, the M bits have no effect, but if MSE=1, the M bits decides mask or unmask of respective interrupts.

4. RIM : Read Interrupt Mask

• This instruction is used to check the status of all pending and maskable interrupts.
• It can also transfer serial data bit from the serial input data line to the D7 bit of the accumulator.
• This instruction transfer the contents of the interrupt control logic and seria control logic to the accumulator. Hence accumulator is loaded with the status fprate after execution of the RIM instruction.
• At a time there can be more than one interrupt request may occur. In such cases if the priority of interrputs is higher then they are serviced.
• The programmer can monitor the status of these pendinginterrupts using RIM instruction.

• Bit D7 is status of SID pin on serial port. When RIm instruction is ecexuted the logic level of SID pin is copied at bit D7.
• Bits D6, D5 and D4 are status of pending interrupts.
• Bits D3 to D0 are status of interrupt enable flip-flop, mask 7.5, mask 6.5 and mask 5.5. When RIm instruction is executed the status of masking is loaded at bit D3 to D0.